1,053 Electrical Engineering jobs in Singapore

Key Responsibilities

• Champion environmental, health, and safety compliance across all electrical operations. Conduct risk assessments and promote a culture of safety and operational discipline.
• Lead commissioning, maintenance, and optimization of electrical systems from 230kV to Low Voltage, including emergency generators, Dynamic UPS, and advanced power quality equipment.
• Provide expert-level support for complex operational issues and lead root cause investigations using 8D problem-solving methodologies.
• Oversee capacity planning, system performance analysis and execution of expansion projects to enable site growth and production demands.
• Review and validate scope, schedule, and cost estimates for infrastructure upgrades. Provide engineering oversight and technical guidance during design and construction phases.
• Conduct risk assessments and failure mode and effects analysis (FMEA) to eliminate single points of failure and enhance system resilience.
• Mentor and develop electrical engineers and technicians through structured training programs and hands-on site engagement.
• Lead post-incident reviews and drive implementation of corrective and preventive actions for system abnormalities.
• Drive strategic initiatives for system capacity expansion, reliability improvement, and energy efficiency.
• Spearhead the deployment of SMART power systems, predictive diagnostics, and digital tools to enhance team productivity and system intelligence.

• Education: Bachelor’s Degree in Electrical Engineering (Master’s preferred).
• Experience: Minimum 8+ years of experience in High, Medium, and Low Voltage Electrical Systems Design, Maintenance, and Operations within semiconductor or advanced manufacturing environments.
• Technical Skills: Must be proficiency in HV/MV/LV systems, ETAP software, and IEC standards. Familiarity with SMART systems and predictive maintenance tools .
• Project Management: Strong organizational and prioritization skills with the ability to manage multiple concurrent initiatives.

At Fab 10 Facilities, you’ll be part of a team supporting cutting-edge technologies like AI, 5G, and autonomous systems. This role offers the chance to contribute meaningfully to strategic projects and infrastructure development in a world-class manufacturing setting.

We value professional growth and offer opportunities for leadership development, technical training, and career advancement. If you’re ready to take on a role that blends engineering expertise with innovations, we welcome your application.

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Responsibilities

• Develop design requirements of an NPU given system level specifications.
• Being part of modelling the performance of the NPU module and its data transaction throughput.
• Microarchitecture design and RTL coding using Verilog / System Verilog HDL for various sub-blocks of the NPU.
• Understanding the mathematics of different convolution operators including different arithmetic formats (fixed point and floating point)
• Estimate, measure and optimize PPA (Performance / Power / Area) to meet key objectives and results.
• Optimizing micro-architecture design for low power and area is required.
• Work closely with verification engineers to ensure comprehensive testing and debug issues.
• Support integration into the overall system, conducting design checks, and addressing lint/timing/CDC issues.
• Collaborate with software teams to assist in compiler and toolchain development and their debugging.
• Produce clear and concise design documentation.

Requirements

• 8+ years of digital design with at least 2 to 3 years of SoC design experience is preferred.
• At least one cycle of NPU design completion experience is required.
• Hands on in digital design experience is a must.
• Preferably has lead a team of at least 3 to 4 people in the past at the capacity of a design lead.
• Experience in microarchitecture design, and RTL coding with Verilog/ System-Verilog.
• Experience in synthesis, with analysis of power, timing and area.
• Disciplined, quality-minded, and highly driven for excellence.
• Excellent team player and good communication skills.
• MSEE/BSEE in Electrical Engineering or Computer Engineering.
• Understanding of convolution operator and number system is required.
• Candidates with relevant experiences would be offered as Senior, taking on higher responsibilities.
• Experience in UVM verification methodology is a plus.
• A plus to have SoC design experience.
• Experience with optimizing micro-architectures for low-power and low-area is a plus.
• Knowledge in deep learning algorithms such as CNN / Transformer is a plus.
• Experience with past design experience with NPU / GPU / DSP design is a plus.
• Experience with ARM or RISC-V processor systems is a plus.
• Passionate and strong in general programming is a plus.

• Seniority level Mid-Senior level

• Employment type Full-time

• Job function Information Technology and Engineering
• Industries Semiconductor Manufacturing

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• Position : Assistant Engineer (Sub-Station Automation) – Up to $3,000 – Alexandra
• Location : Alexandra
• Working hours : 5 Days Work Week – Monday to Friday: 8AM to 5PM / 8.30AM to 5.30PM / 9AM to 6PM / 9.30AM to 6.30PM / 10AM to 7PM
• Salary (commensurate with experience) : Up to $,000 Basic + Midnight Allowance + OT + AWS + Performance Bonus (Up to 3 Months) + Medical Benefits ( 500/year) with Dependents Coverage + 14 - 17 Days Annual Leave + Company Activities + Company Trips
• Duration : Perm / 2 Years Contract (Renewable or Convertible to Perm)
• Industry : Automation

Responsibilities:

• Planning, coordinating, and executing substation automation projects.
• Designing, costing, and integrating substation automation systems based on project requirements.
• Installing, testing, and troubleshooting substation automation systems on-site.
• Preparing project documentation and drawings.

Requirements:

• Minimum Nitec in Electrical Engineering/Computer Engineering or related qualifications
• Knowledge of data communication and automation systems for electrical networks
• No experience welcome too, training will be provided!
• Bilingual in English and Mandarin to converse with Mandarin speaking associates

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Jeslyn Tan

Associate Consulting Director (APAC)

Reg no.: R | EA No: 13C6684

Thank you for your interest in this position. Our shortlisting period is 3 working days. Only shortlisted candidates will be contacted for further consideration.

If you do not receive communication from us within this timeframe, it's likely that your application has not been shortlisted by our client. In such cases, we recommend that you continue your job search to maximize your opportunities. We wish you all the best and should we have any suitable roles that match your experiences/ qualifications/ preferences, we will reach out to you.

Our vision is to transform how the world uses information to enrich life for all.

Join an inclusive team passionate about one thing: using their expertise in the relentless pursuit of innovation for customers and partners. The solutions we build help make everything from virtual reality experiences to breakthroughs in neural networks possible. We do it all while committing to integrity, sustainability, and giving back to our communities. Because doing so can fuel the very innovation we are pursuing.

Welcome! As a NAND Design Rule Engineer in Process Integration (Technology Development Group), your primary role is to drive and contribute to next generation Advanced NAND development efforts. You will be working with several peer groups to define, implement, and coordinate effective actions to enable multiple projects to hit key achievements and timelines.

• Responsible for Design rule release, Design Rule check waivers, Mask and related DRC definitions, Mask review and sign off, Process Requirement Specifications, etc. for R&D and Production Designs
• Drive/Contribute to deliver key milestones starting from Project Kick Off till End of Life
• Collaborate with a network of stakeholders including Process Integration, Advanced Mask Design, Scribe & Frame, Layout & Design and Quality & Reliability to help direct development efforts for a new Advanced NAND generation
• Ensure the quality of DRCs (Design Rule Checks) released with appropriate reaction to deviation from established design rules and proper documentation
• Work with Yield Enhancement, Product Engineers, Defect analysis, and Quality Assurance teams to understand process issues related to the database layout, and prioritize development of solutions with Process Integration, Advanced Mask Design, Scribe & Frame, Layout & Design
• Help design and evaluate test structures to provide data for next generation devices and to quantify process margin on current devices
• Summarize complex problems, derive, and explain actions taken to address them
• Drive effective multi-functional communication on issue resolution, and support across node Design Rule alignment
• Define sub-milestones for the project within the layout schedule and work with the various teams to achieve the targets and timelines
• Ensure the best possible communication between NAND Design Rule and other key stakeholders
• Enthusiastically identify and address process issues and process window vs. die size conflicts stemming from specific database layout or layout techniques
• Assure timely documentation and feedback of R&D activities regarding design rule improvements to production parts still in design phase.

what sets you Apart

• 5 years of experience in semiconductor industry in the areas Process Integration, Yield Enhancement, Product Engineering, Test Structure Development, or Unit Process Development
• Exposure to design & layout, ability to do minor layout and experience with CAD tools like Cadence Virtuoso, K2view, and Mentor Graphics DRV/RVE is highly desired
• Proven capability to successfully resolve sophisticated issues
• Understanding of Advanced NAND process flow, as well as the function and purpose of major NAND components, such as BL sensing, Word-line driver, CMOS under array, etc.
• Familiarity with CAD group interactions, data post-processing, and the process of transferring data from the database to the reticle

Master's Degree or higher in Electrical Engineering, Microelectronics, Physics, or related field with 5 years of experience in semiconductor industry or Bachelor's Degree plus 8 years' experience will also be considered.

About Micron Technology, Inc.

We are an industry leader in innovative memory and storage solutions transforming how the world uses information to enrich life for all . With a relentless focus on our customers, technology leadership, and manufacturing and operational excellence, Micron delivers a rich portfolio of high-performance DRAM, NAND, and NOR memory and storage products through our Micron and Crucial brands. Every day, the innovations that our people create fuel the data economy, enabling advances in artificial intelligence and 5G applications that unleash opportunities — from the data center to the intelligent edge and across the client and mobile user experience.

To learn more, please visit micron.com/careers

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.

To request assistance with the application process and/or for reasonable accommodations,please contact

Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.

Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.

AI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.

Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.

Regional Data Center Engineering Director (Electrical focus)

Direct message the job poster from First Point Group

Our client is a leading Data Center operator working closely with hyperscalers across APAC, expanding aggressively (beyond 200MW expansion in plan for the next couple of years), currently seeking for a Regional Data Center Senior MEP Director, ideally with a keen focus on Electrical Design and Engineering. They are working with most of the leading hyperscalers and have around a billion USD in funding to help their rapid expansion.

As the Regional Data Center Engineering Director, you are responsible for leading the Group’s Data Center development and spearheading design, construction and build of Greenfield + Brownfield Data Center. The successful candidate will be strong in Data Center Mechanical and Electrical Design and Engineering (particularly Electrical) with good knowledge in finance to oversee project cost and management.

Responsibilities

• Lead, mentor, and support a team of project managers, engineering managers, and energy managers.
• Foster a high-performance culture and promote creativity, collaboration, and innovation.
• Recruit top engineering and project management talent.

• Serve as part of the senior staff, collaborating across departments and divisions.
• Participate in strategic planning with stakeholders (Product Management, Operations, Finance, etc.) to meet business outcomes.
• Prepare and present business cases to top executive management and stakeholders.

• Oversee greenfield and brownfield projects, including site selection, team setup, design, tender award, and construction.
• Engage and manage best-in-class consultant teams (e.g., architects, M&E, C&S, energy specialists).
• Ensure on-time and to-specification delivery of data centers.

• Lead research and development projects to improve DC energy and water efficiency, build efficiency, and sustainability.
• Drive initiatives to lower PUE (Power Usage Effectiveness), WUE (Water Usage Effectiveness), and carbon emissions.
• Conduct technical assessments, feasibility studies, and new technology evaluations.

• Develop strategies for DC configuration and sizing.
• Identify land parcels, finalize designs, evaluate power sources, and ensure network connectivity.
• Collaborate with the Product department to customize projects based on customer requirements.

• Drive energy, water, and waste efficiency initiatives for both existing and new DCs.
• Promote the use of green power and sustainable practices.

• 10+ years of relevant experience in data centre related works involving DC development and engineering works.
• Bachelor’s degree or above in Mechanical, Electrical, Project Management, Architecture or related disciplines.
• Strong Mechanical and Electrical background with ability to lead design requirement, identify SPOF, oversee engineering fault analysis and ability to solve complex engineering problems such as cooling, power, etc.
• Good financial knowledge to oversee project cost control and management

• Director

• Full-time

• Engineering, Project Management, and Design

• Construction, Building Construction, and Engineering Services

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Senior Embedded Systems Engineer (Systems on Chip)

DSO National Laboratories (DSO) is Singapore's largest defence research and development (R&D) organisation, with the critical mission to develop technological solutions to sharpen the cutting edge of Singapore's national security. At DSO, you will develop more than just a career. This is where you will make a real impact and shape the future of defence across the spectrum of air, land, sea, space and cyberspace.

The Sensors Division undertakes research and development in a wide range of sensor technologies, including radar, acoustics and electro-optics to provide the SAF with a recognised battlefield situation picture.

People are DSO’s greatest asset. You will get to realise your career aspirations and develop your own niche either as a deep technical expert or a leader in the team. With frequent career dialogues and a robust training and development framework, we will provide you with the necessary development tools for you to reach your potential. You will also be recognised and rewarded through competitive remuneration packages and scholarship opportunities.

• Design and develop embedded systems based on advanced SoCs, including RFSoC, Xilinx Versal Adaptive Compute Acceleration Platform, and PolarFire
• Translate high-level product and system requirements into detailed subsystem and architectural specifications
• Propose, scope, and prioritize engineering tasks to drive successful project outcomes
• Collaborate with cross-functional teams to implement, validate, and optimize embedded solutions
• Apply signal processing techniques to meet product performance requirements
• Perform methodical debugging and root cause analysis across hardware and software boundaries
• Ensure adherence to industry best practices in SoC design flows, verification, and validation
• Mentor junior engineers and provide technical guidance to the team

• Masters / Bachelor’s Degree in Electrical and Electronic Engineering / Computer Engineering
• Proficiency in embedded C/C++, HDL (VHDL/Verilog), and SoC toolchains
• Experience with SoC design flows, FPGA/SoC synthesis, simulation, and verification tools
• Strong debugging and root-cause analysis skills across hardware/software boundaries
• Familiarity with signal processing algorithms and real-time implementation
• Experience with advanced SoCs (Xilinx RFSoC, Intel RF SoC, etc.) and diverse chipsets (e.g., PolarFire)
• Ability to translate product requirements into detailed technical specifications and vice versa
• Strong systems-thinking mindset with ability to decompose designs into subsystems
• Knowledge of industry best practices in embedded design, testing, and validation
• Leadership capability to propose technical direction and mentor team members

• Mid-Senior level

• Full-time

• Other

• Defense and Space Manufacturing

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Overview

The Silicon Platform Team acts as the core R&D middleware group for chip development within the company. The team covers the full spectrum of the chip design flow, including Logic Synthesis, Design for Testability (DFT), Backend Design, Physical and STA (Static Timing Analysis) Signoff, as well as Power Integrity, IR drop, and Electromagnetic Compatibility (Power/IR/EM). The team also oversees tape-out, mass production, packaging, testing, and board-level verification. They collaborate closely with front-end chip teams across business units to drive R&D progress and mass production deployment for chip.

• Responsible for the block/chip level physical design, from Netlist to GDSII, including Floorplan, Auto Place and Routing, PPA push and signoff work such as Physical Verification / STA / IREM etc.
• As the foundry contact window, participate in new process introduction, chip tapeout, mass production, packaging and testing, quality control, and other tasks.
• Participate in project plan evaluation and project initiation preparation.

Minimum Qualifications

• Bachelor's degree or above, graduated from relevant majors such as microelectronics/computer, with more than 2 years of APR work experience.
• Have proficient scripting skills (e.g., TCL, Perl, Python, etc.).
• Proficiently use mainstream backend tools and master basic backend concepts.
• Have project experience with advanced processes, such as 7nm/5nm/3nm.

Preferred Qualifications

• Good teamwork spirit and a serious and responsible work attitude.
• Good communication skills, with fluent English reading and writing abilities.

• Mid-Senior level

• Full-time

• Engineering and Information Technology

• Technology, Information and Internet

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Responsibilities

• Implement ISP Algorithm into hardware using Verilog, SystemVerilog, and/or SystemC (High Level Synthesis).
• Define ISP hardware architecture based on product features, performance requirements, gate count, and power estimation.
• Verify logic at ISP and digital system levels.
• Optimize design for reduced gate count and low power consumption.
• Collaborate closely with the ISP Algorithm team on design activities.

Requirements

• Minimum MSEE, BSEE, or equivalent, with 3+ years of digital design and verification experience.
• Knowledge of CMOS Image Sensors and image signal processing (ISP).
• Experience with SystemC/C++, SystemVerilog, and Catapult HLS tool.
• Strong debugging and problem-solving skills.
• Good communication and interpersonal skills.
• Result-oriented with adaptable behavior.

• Associate

• Full-time

• Semiconductor Manufacturing

Responsibilities:

• Work closely with design engineers and architects to create and document detailed test plans for verifying the SoC design.
• Establish and manage the infrastructure and environment for automated verification of the SoC's architecture, functionality, and performance.
• Develop reusable testbenches, test cases using constrained-random and directed methods, and verification modules for both block and system levels.
• Create a regression strategy, methodology, and scripting tools, ensuring comprehensive function coverage and addressing verification gaps before design releases and tape-out.
• Collaborate with design engineers to troubleshoot and resolve simulation issues.
• Provide support to test engineers during post-silicon validation.
• Mentor and guide team members and junior engineers, aiming to enhance verification efficiency.
  

Requirements:

• Master in Electrical Engineering or equivalent with 8 years of relevant working experience/ PhD in Electrical Engineering or equivalent with 3 years working experience.
• Extensive understanding of UVM/OVM, Semiformal Verification, assertion-based verification, and hardware-software co-verification methodology.
• Skilled in Verilog, SystemVerilog, Python, Perl, TCL, Shell scripting, C/C++, SystemC, and assembly coding for industry-standard ISAs.
• Familiar with MIPI, AMBA (APB/AHB/AXI) bus protocols, RISC-V/ARM, or DSP cores.
• Experience in verifying designs at RTL and post-P&R gate levels.

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HOW TO APPLY :

Interested candidates, please submit your resume by clicking on “Quick Apply” or contact for more details.

Please provide following information in the resume for immediate processing

1) Reasons for leaving current and/or last employment

2) Last drawn and/or current salary

3) Expected salary

4) Date of availability and/or Notice Period

All applications will be treated in strictest confidence and only shortlisted candidates will be notified

Wee Wai Dan

EA License No : 03C5391

EA Reg No : R