146 Ic Design Engineer jobs in Singapore

Designs and develops integrated circuits. Oversees definition, design, verification, and documentation for ASIC development. Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation. Contributes to the development of multidimensional designs involving the layout of complex integrated circuits. Evaluates all aspects of the process flow from high-level design to synthesis, place and route, and timing and power use. Analyzes equipment to establish operation data, conducts experimental tests, and evaluates results. May also review vendor capability to support development.

• Knowledge: Internally recognized technical or business contributor uses skills to contribute to development of company objectives and principles and to achieve goals in creative and effective ways.

• Experience : Bachelors and 12+ years of related experience; at this level a post-graduate degree is typically expected or Masters degree and 10+ years of related experience or PhD and 7+ years of related experience

• Possesses a specialized level of technical expertise or business acumen with accomplished track record

• Networked within the industry and acknowledged expert by peers
• Represents the company at industry forum and conferences
• Develop and/or applies innovative technologies and concepts
• Technical or business consulting resource to business level managers
• Job Complexity / Contribution : Works on advanced complex technical projects or business issues requiring state of the art technical knowledge or industry. Recognized as the in-house expert on specific technologies.
• May manage resources to achieve group objectives
• Decisions have major impact on organization, both internally and externally
• Supervision : Goals generally communicated in "solution" or project goal terms. Means of arriving at a solution not generally determined by other than the incumbent.
• Sets direction for high-impact and/or long-range strategic/technical projects
• Leads major initiatives/projects
• Virtually self-supervisory

Our company seeks a skilled IC Design Engineer to develop low power and multi-clock domain designs.

• Write Verilog code for Low Power and Multi-Clock Domain Designs.
• Perform synthesis, pre-and-post-layout timing closure, and front-end design flow such as Synthesis, power analysis, and normal check etc.
• Collaborate with application and product engineering teams to evaluate the design.
• Provide detailed documentation, descriptions, and information to engineers and customers.

• Major in Electrical Engineering or Computer Science; Master Degree with 2+ years or Bachelor with 4+ years working experiences in ASIC design.
• Proficient in Verilog and RTL design.
• Strong problem-solving and communication skills.
• Excellent written and spoken English to collaborate with global teams.
• Familiarity with System-Verilog and UVM verification methodology is a plus.
• Knowledge of script languages (perl, tcl etc.) is a plus.
• Understanding of STA timing flow is a plus.

• Develop and implement micro-architecture for complex digital blocks.
• Write synthesizable RTL code in Verilog/SystemVerilog for various IPs and SoCs.
• Perform linting, CDC (Clock Domain Crossing), and low-power checks (UPF/CPF).
• Conduct logic synthesis, timing constraints generation, and timing closure support.
• Collaborate with verification engineers to define test plans and ensure design quality.
• Support pre-silicon validation and post-silicon bring-up and debug activities.
• Create and maintain technical documentation.

• Bachelor's or Master's degree in Electrical/Electronics Engineering or a related field.
• Proven experience in ASIC design flow and methodologies.
• Strong proficiency in RTL coding using Verilog or SystemVerilog.
• Hands-on experience with synthesis, timing analysis, and scripting languages (e.g., TCL, Python).
• Knowledge of low-power design techniques and power integrity issues is a plus.
• Familiarity with industry-standard EDA tools from Synopsys, Cadence, or Siemens.
• Excellent problem-solving skills and a strong team-oriented mindset.
• Effective communication skills and the ability to work in a dynamic, global team environment.

Job Overview:

NSING is seeking a highly motivated and skilled IC Design Engineer with expertise in Backend Place and Route (P&R) to join our team. The successful candidate will be responsible for physical design implementation, including SoC top level floorplanning, placement, clock tree synthesis, routing, timing closure, and signoff for complex SoCs, ASICs, or custom ICs. You will collaborate closely with RTL designers, DFT engineers, and other cross-functional teams to ensure high-performance, power-efficient, and manufacturable designs.

Key Responsibilities:

Place and Route Execution:

• Perform SoC top level floor-planning, power plan design, placement of IP blocks and pads & Analog blocks, implement efficient clock tree synthesis (CTS), and routing for complex IC designs.
• Low Power P&R with multiple power domains with power switches and isolation cells
• Handle timing closure, including setup, hold, signal integrity, and cross-talk noise management.
• Perform physical verification (DRC, LVS) and resolve design rule violation.

Optimization:

• Optimize designs for power, performance, and area (PPA).
• Use EDA tools to achieve optimal routing, minimize congestion, and manage IR drop and electromigration.
• Collaboration and Signoff:
• Work closely with RTL design, synthesis, DFT, and packaging teams to ensure smooth handoffs and integration.
• Perform static timing analysis (STA) and work on timing closure at multiple corners and modes.
• Collaborate on tapeout activities, including final signoff checks (timing, power, physical verification).
• EDA Tools and Scripting:
• Use industry-standard tools such as Cadence Innovus, Synopsys ICC2, Mentor Calibre, and others.
• Develop and maintain automation scripts using TCL, Perl, or Python to streamline the P&R workflow.
• Documentation and Reporting:
• Generate reports and documentation on P&R progress, challenges, and metrics.
• Participate in design reviews and provide feedback on design trade-offs.

Experience:

• Min of 5 years of experience in IC physical design, including hands-on SoC level P&R in advanced nodes (at least 40 nm and below )
• Strong background in CTS , timing closure, power grid design, pad placement , analog/digital placements, and physical verification.

Technical Skills:

• Proficiency in EDA tools like Cadence Innovus, Synopsys ICC2, or similar.
• Familiarity with scripting languages (TCL, Perl, Python) for automation.integrity, and low-power design techniques.
• Familiarity with scripting languages (TCL, Perl, Python) for automation.
• Knowledge of DRC, LVS, and physical signoff methodologies.

Soft Skills:

• Strong analytical, problem-solving, and debugging skills.
• Excellent communication skills and ability to work in cross-functional teams.

Preferred Qualifications:

• A plus with experience normal CMOS with additional advanced FinFET technology nodes , Full depletion FDSOI with Back-bias and Forward Bias voltage technology
• Experience with EM/IR drop analysis and mitigation will be an added advantage.

Key Responsibilities:

• Develop and implement micro-architecture for complex digital blocks.
• Write synthesizable RTL code in Verilog/SystemVerilog for various IPs and SoCs.
• Perform linting, CDC (Clock Domain Crossing), and low-power checks (UPF/CPF).
• Conduct logic synthesis, timing constraints generation, and timing closure support.
• Collaborate with verification engineers to define test plans and ensure design quality.
• Support pre-silicon validation and post-silicon bring-up and debug activities.
• Create and maintain technical documentation.

Qualifications and Skills:

• Bachelor's or Master's degree in Electrical/Electronics Engineering or a related field.
• Proven experience in ASIC design flow and methodologies.
• Strong proficiency in RTL coding using Verilog or SystemVerilog.
• Hands-on experience with synthesis, timing analysis, and scripting languages (e.g., TCL, Python).
• Knowledge of low-power design techniques and power integrity issues is a plus.
• Familiarity with industry-standard EDA tools from Synopsys, Cadence, or Siemens.
• Excellent problem-solving skills and a strong team-oriented mindset.
• Effective communication skills and the ability to work in a dynamic, global team environment.

Key Responsibilities:

• Develop and implement micro-architecture for complex digital blocks.

• Write synthesizable RTL code in Verilog/SystemVerilog for various IPs and SoCs.

• Perform linting, CDC (Clock Domain Crossing), and low-power checks (UPF/CPF).

• Conduct logic synthesis, timing constraints generation, and timing closure support.

• Collaborate with verification engineers to define test plans and ensure design quality.

• Support pre-silicon validation and post-silicon bring-up and debug activities.

• Create and maintain technical documentation.

Qualifications and Skills:

• Bachelor's or Master's degree in Electrical/Electronics Engineering or a related field.

• Proven experience in ASIC design flow and methodologies.

• Strong proficiency in RTL coding using Verilog or SystemVerilog.

• Hands-on experience with synthesis, timing analysis, and scripting languages (e.g., TCL, Python).

• Knowledge of low-power design techniques and power integrity issues is a plus.

• Familiarity with industry-standard EDA tools from Synopsys, Cadence, or Siemens.

• Excellent problem-solving skills and a strong team-oriented mindset.

Key Responsibilities:

• Develop and implement micro-architecture for complex digital blocks.

• Write synthesizable RTL code in Verilog/SystemVerilog for various IPs and SoCs.

• Perform linting, CDC (Clock Domain Crossing), and low-power checks (UPF/CPF).

• Conduct logic synthesis, timing constraints generation, and timing closure support.

• Collaborate with verification engineers to define test plans and ensure design quality.

• Support pre-silicon validation and post-silicon bring-up and debug activities.

• Create and maintain technical documentation.

Qualifications and Skills:

• Bachelor’s or Master’s degree in Electrical/Electronics Engineering or a related field.

• Proven experience in ASIC design flow and methodologies.

• Strong proficiency in RTL coding using Verilog or SystemVerilog.

• Hands-on experience with synthesis, timing analysis, and scripting languages (e.g., TCL, Python).

• Knowledge of low-power design techniques and power integrity issues is a plus.

• Familiarity with industry-standard EDA tools from Synopsys, Cadence, or Siemens.

• Excellent problem-solving skills and a strong team-oriented mindset.

Key Responsibilities:

• Develop and implement micro-architecture for complex digital blocks.
• Write synthesizable RTL code in Verilog/SystemVerilog for various IPs and SoCs.
• Perform linting, CDC (Clock Domain Crossing), and low-power checks (UPF/CPF).
• Conduct logic synthesis, timing constraints generation, and timing closure support.
• Collaborate with verification engineers to define test plans and ensure design quality.
• Support pre-silicon validation and post-silicon bring-up and debug activities.
• Create and maintain technical documentation.

Qualifications and Skills:

• Bachelor’s or Master’s degree in Electrical/Electronics Engineering or a related field.
• Proven experience in ASIC design flow and methodologies.
• Strong proficiency in RTL coding using Verilog or SystemVerilog.
• Hands-on experience with synthesis, timing analysis, and scripting languages (e.g., TCL, Python).
• Knowledge of low-power design techniques and power integrity issues is a plus.
• Familiarity with industry-standard EDA tools from Synopsys, Cadence, or Siemens.
• Excellent problem-solving skills and a strong team-oriented mindset.
• Effective communication skills and the ability to work in a dynamic, global team environment.