138 Ic Design Engineer jobs in Singapore

• Develop and Review Test Plan based on IC design specification
• Develop constrained-Random verification environment for complex DUT
• Develop/Modify Testbenches and test programmes using UVM-SV for Pre-Silicon IP/ICs/SOCs and ensure product meet their performance
• Implement coverage matrix using cover point and assertion
• Create and debug tests for DUT
• Resolve bugs with remote designers

• Bachelor/Masters Degree in Electrical/Electronics/Computer Engineering with 1 year or more experience
• Hands-on experience in Silicon/ IP verification using SystemVerilog/ UVM
• Strong understanding of verification process from test plan to coverage completion
• Strong communication and Analytical skills
• Understanding of HDL (Verilog, VHDL)
• Experience in using leading EDA software tools like Cadence/ Synopsys

• Design and Develop ICs using leading EDA software; work on RTL to GDS, including synthesis, layout, floor planning, placement, clock tree insertion and routing.
• Responsible for GDS validation like DRC/LVS, timing closure sign-off, scan, validation etc.
• Design, implement and maintain synthesis, DFT and Static Timing Analysis scripts using best-in-class methodologies.
• Work closely with other groups like Analog Design, Systems, Applications and Production in determining architecture and specification of the products.

• Bachelor/Masters Degree in Electronics/Electrical/Computer Engineering with min 1 year experience
• Good experience and knowledge in design flow from Netlist to GDS, Synthesis, layout, Floor Planning, route , STA, CTS, RC Extraction and correlation
• Static timing analysis, power and noise analysis and back-end verification across multiple projects.
• Proficient with backend design EDA tools, Synopsys ICC2 preferred
• Successfully track records of taping out complex SOC
• Working knowledge of deep sub-micron routing issues as they relate to power and timing.
• Proficiency using Perl and TCL
• Self-motivated team worker, good verbal and written communication skills

• Develop and Review Test Plan based on IC design specification
• Develop constrained-Random verification environment for complex DUT
• Develop/Modify Testbenches and test programmes using UVM-SV for Pre-Silicon IP/ICs/SOCs and ensure product meet their performance
• Implement coverage matrix using cover point and assertion
• Create and debug tests for DUT
• Resolve bugs with remote designers

• Bachelor/Masters Degree in Electrical/Electronics/Computer Engineering with min 1 year of experience
• Hands-on experience in Silicon/ IP verification using SystemVerilog/ UVM
• Strong understanding of verification process from test plan to coverage completion
• Strong communication and Analytical skills
• Understanding of HDL (Verilog, VHDL)
• Experience in using leading EDA software tools like Cadence/ Synopsys

Job Description

• Design and Develop ICs using leading EDA software; work on RTL to GDS, including synthesis, layout, floor planning, placement, clock tree insertion and routing.
• Responsible for GDS validation like DRC/LVS, timing closure sign-off, scan, validation etc.
• Design, implement and maintain synthesis, DFT and Static Timing Analysis scripts using best-in-class methodologies.
• Work closely with other groups like Analog Design, Systems, Applications and Production in determining architecture and specification of the products.

Job Requirements

• Bachelor/Masters Degree in Electronics/Electrical/Computer Engineering with 1 year or more experience
• Good experience and knowledge in design flow from Netlist to GDS, Synthesis, layout, Floor Planning, route , STA, CTS, RC Extraction and correlation
• Static timing analysis, power and noise analysis and back-end verification across multiple projects.
• Proficient with backend design EDA tools, Synopsys ICC2 preferred
• Successfully track records of taping out complex SOC
• Working knowledge of deep sub-micron routing issues as they relate to power and timing.
• Proficiency using Perl and TCL
• Self-motivated team worker, good verbal and written communication skills

Ethos Search Associates

EA Licence No: 13C6655

EA Reg No: R Rose

Job Descriptions

• Develop and Review Test Plan based on IC design specification
• Develop constrained-Random verification environment for complex DUT
• Develop/Modify Testbenches and test programmes using UVM-SV for Pre-Silicon IP/ICs/SOCs and ensure product meet their performance
• Implement coverage matrix using cover point and assertion
• Create and debug tests for DUT
• Resolve bugs with remote designers

Requirements

• Bachelor/Masters Degree in Electrical/Electronics/Computer Engineering with min 1 year of experience
• Hands-on experience in Silicon/ IP verification using SystemVerilog/ UVM
• Strong understanding of verification process from test plan to coverage completion
• Strong communication and Analytical skills
• Understanding of HDL (Verilog, VHDL)
• Experience in using leading EDA software tools like Cadence/ Synopsys

• Lead the analog development of either DDR or PLL (any one), collaborating with other departments to complete the full IP development cycle.
• Support the mass production and debugging of the assigned IP.
• Participate in the development of other SerDes IPs and coordinate related product activities.

• Master's degree or above in Electronic Engineering or Microelectronics, with over 5 years of experience in analog design;
• At least 3 years of hands-on experience in DDR or PLL design;
• Capable of independently managing projects with solid tape-out experience.
• Experience with FinFET process is preferred.
• Proactive, detail-oriented, responsible, with a positive work attitude and good communication skills;
• A strong team player;

Flamingo Recruitment Pte Ltd

EA License : 21C0588

Job Descriptions

• Develop and Review Test Plan based on IC design specification
• Develop constrained-Random verification environment for complex DUT
• Develop/Modify Testbenches and test programmes using UVM-SV for Pre-Silicon IP/ICs/SOCs and ensure product meet their performance
• Implement coverage matrix using cover point and assertion
• Create and debug tests for DUT
• Resolve bugs with remote designers

Requirements

• Bachelor/Masters Degree in Electrical/Electronics/Computer Engineering with 1 year or more experience
• Hands-on experience in Silicon/ IP verification using SystemVerilog/ UVM
• Strong understanding of verification process from test plan to coverage completion
• Strong communication and Analytical skills
• Understanding of HDL (Verilog, VHDL)
• Experience in using leading EDA software tools like Cadence/ Synopsys

Ethos Search Associates Pte. Ltd.

EA Licence No: 13C6655

EA Reg No: R Rose

• Develop and Review Test Plan based on IC design specification
• Develop constrained-Random verification environment for complex DUT
• Develop/Modify Testbenches and test programmes using UVM-SV for Pre-Silicon IP/ICs/SOCs and ensure product meet their performance
• Implement coverage matrix using cover point and assertion
• Create and debug tests for DUT
• Resolve bugs with remote designers
Requirements
• Bachelor/Masters Degree in Electrical/Electronics/Computer Engineering with 1 year or more experience
• Hands-on experience in Silicon/ IP verification using SystemVerilog/ UVM
• Strong understanding of verification process from test plan to coverage completion
• Strong communication and Analytical skills
• Understanding of HDL (Verilog, VHDL)
• Experience in using leading EDA software tools like Cadence/ Synopsys
Ethos Search Associates Pte. Ltd.
EA Licence No: 13C6655
EA Reg No: R Rose

• Lead the analog development of either DDR or PLL (any one), collaborating with other departments to complete the full IP development cycle.
• Support the mass production and debugging of the assigned IP.
• Participate in the development of other SerDes IPs and coordinate related product activities.

• Master’s degree or above in Electronic Engineering or Microelectronics, with over 5 years of experience in analog design;
• At least 3 years of hands-on experience in DDR or PLL design;
• Capable of independently managing projects with solid tape-out experience.
• Experience with FinFET process is preferred.
• Proactive, detail-oriented, responsible, with a positive work attitude and good communication skills;
• A strong team player;

Flamingo Recruitment Pte Ltd

EA License : 21C0588