82 Digital Ic Design jobs in Singapore

As a seasoned digital IC design expert, you will be responsible for collaborating with architects to discuss and optimize System on Chip (SoC) architecture.

Key Responsibilities:

• Collaborate with architects to discuss and optimize SoC architecture, including SoC integration, system block development, power management, clock/reset, system register, test control, PinMux, and more.
• Work closely with architects and Application Processors to create an optimized SoC floorplan, perform SoC power checks, review SoC timing constraints, provide SoC Design for Testability support, and develop a SoC verification plan.

Requirements:

• Bachelor's or Master's Degree in Electronic Engineering with experience in ASIC design.
• Proficiency in the ASIC design flow.
• Strong background in RTL coding, RTL and gate-level simulation, logic synthesis, static timing analysis, timing closure, and verification.
• Good understanding of Design for Testability.
• Familiarity with UNIX/Linux environment and scripting.
• Excellent communication and interpersonal skills.
• Strong analytical and problem-solving skills.

Benefits:

Our company offers a dynamic work environment that fosters growth and collaboration. We encourage motivated and detail-oriented individuals with a passion for digital IC design to apply.

Other Opportunities:

We strive to create a culture of innovation and excellence, where our employees can thrive and contribute to the success of our organization.

• Work on SoC architecture discussion and optimization with architect; SoC integration; system block development, e.g., power management, clock/reset, system register, test control, PinMux, etc;
• Work on SoC floorplan with architect and APR; SoC power check; SoC timing constraints and review support; SoC DFT support; SoC verification plan and SoC verification support.

• Bachelor's or Master's Degree in Electronic Engineering with ASIC design experience.
• Experience with ASIC design flow.
• Experience in RTL coding, RTL and gate-level simulation, logic synthesis, static timing analysis, timing closure and verification.
• Good understanding of DFT.
• Familiarity with UNIX/Linux environment and scripting.
• Good communication and interpersonal skills.
• Strong analytical and problem-solving skills.

Senior IC Mixed Signal Engineer

This is a high-profile position in the field of digital IC/ASIC design. We are seeking an exceptional engineer with expertise in designing and integrating digital subsystems and IPs for SoCs. The ideal candidate will have a strong background in RTL development (Verilog/SystemVerilog), hands-on experience with SoC integration, and familiarity with verification flows (UVM/SVA) synthesis STA, and physical implementation.

• The successful candidate will be responsible for developing and integrating digital subsystems and IPs for SoCs including memory wrappers, DSP logic, calibration modules, controllers, and other related components.
• They will also own the RTL design from architecture definition to silicon validation ensuring that the designed systems meet the required performance, power, and area efficiency targets.
• The role requires close collaboration with DV teams on UVM/SVA-based verification debugging and test regression.

1. Develop and integrate digital subsystems and IPs for SoCs.
2. Own RTL design from architecture definition to silicon validation.
3. Work closely with DV teams on UVM/SVA-based verification debugging and test regression.
4. Support silicon bring-up and troubleshooting bridging design and firmware.
5. Cross-functionally collaborate on mixed-signal integration and hardware/software co-design.
6. Explore and implement design optimizations for performance, power, and area efficiency.

• Bachelor's, Master's, or PhD in Electrical/Electronic/Computer Engineering.
• At least 5+ years of experience in digital IC/ASIC design with at least 2-3 successful tape-outs.
• Strong RTL development skills (Verilog/SystemVerilog) and hands-on SoC integration.
• Familiarity with verification flows (UVM/SVA) synthesis STA, and physical implementation.

You will be part of a small but highly skilled team where your contributions have direct impact from design to silicon. You'll have exposure to cutting-edge IC design flows, advanced process nodes, and global collaborations while working in a supportive environment that encourages innovation, ownership, and career growth.

JOB DESCRIPTION

• Discussion with system engineers on SoC architecture and feedback on optimization.
• Work on SoC integration; system block development, e.g., power management, clock/reset, system register, test control, PinMux, etc;
• Discussion with synthesis engineer and back-end engineer on design optimization.
• SoC DFT support;
• SoC verification plan and SoC verification support

JOB REQUIREMENTS

• Bachelor's or Master's Degree in Electronic Engineering with ASIC design experience.
• Knowledge of ASIC design flow
• Experience in RTL coding, RTL and gate-level debug
• Understanding of DFT, timing and power requirements
• Familiar with UNIX/ Linux environment and scripting
• Good communication and interpersonal skills
• Strong analytical and problem-solving skills
• Knowledge on mixed-signal design would be an advantage.

JOB DESCRIPTION

• Discussion with system engineers on IP requirement and micro architecture.
• Develop IP (control path intensive or data path intensive) meet functional requirement and protocol standard.
• Support SoC designer on integration, timing constraints and power domain setting.
• Support IP verification for verification plan review, test case debugging.

JOB REQUIREMENTS

• Bachelor's or Master's Degree in Electronic Engineering with ASIC design experience.
• Experience in IP development (either control path intensive or data path intensive).
• Knowledge of timing, DFT and power structure.
• Familiar with UNIX/ Linux environment and scripting.
• Experience on communication IP and/or video IP development would be advantage.
• Good communication and interpersonal skills.
• Strong analytical and problem-solving skills.
• Experience on communication IP development would be an advantage.
• Experience on video IP development would be an advantage.

JOB DESCRIPTION

• Work with system engineers on timing requirements and feedback on optimization.
• Work on SoC timing constraint, synthesis and timing closure.
• Work on power structure, eg. Isolation of power domains, level-shifter crossing voltage domains
• Conduct formal verification for release comparison.
• Support back-end implementation on timing violation analysis and fix.
• Support scan insertion and optimization.
• Support on power structure and power optimization.

JOB REQUIREMENTS

• Bachelor's or Master's Degree in Electronic Engineering with ASIC design experience.
• Familiar with ASIC design flow
• Experience in logic synthesis, static timing analysis, timing closure
• Good understanding of DFT and Power structure.
• Familiar with UNIX/ Linux environment and scripting
• Good communication and interpersonal skills

Job Summary

• Collaborate with system engineers to ensure optimal timing requirements and provide constructive feedback for optimization.
• Develop and implement SoC timing constraints, synthesis, and timing closure strategies.
• Design and optimize power structures, including isolation of power domains and level-shifter crossings for voltage domain transitions.
• Perform formal verification for release comparison and analysis.
• Support back-end implementation teams in resolving timing violations and facilitating fixes.
• Assist in scan insertion and optimization processes.
• Contribute to power structure and power optimization efforts.

Key Responsibilities

• Hold a Bachelor's or Master's Degree in Electronic Engineering with significant ASIC design experience.
• Be familiar with the ASIC design flow and possess relevant knowledge.
• Have expertise in logic synthesis, static timing analysis, and timing closure techniques.
• Demonstrate a good understanding of Design for Testability (DFT) and power structure principles.
• Be proficient in UNIX/Linux environments and scripting languages.
• Exhibit strong communication and interpersonal skills.
• Display analytical and problem-solving abilities.

• Collaborate with system engineers on SoC architecture and provide feedback on optimization.
• Work on SoC integration, including system block development such as power management, clock/reset, system register, test control, PinMux, etc.
• Discuss design optimization with synthesis and back-end engineers.
• Provide SoC DFT support.
• Develop and implement SoC verification plans and provide verification support.

• Bachelor's or Master's Degree in Electronic Engineering with experience in ASIC design.
• Knowledge of ASIC design flow.
• Experience in RTL coding, RTL and gate-level debug.
• Understanding of DFT, timing and power requirements.
• Familiarity with UNIX/Linux environment and scripting.
• Excellent communication and interpersonal skills.
• Strong analytical and problem-solving skills.
• Knowledge of mixed-signal design is an advantage.

• Write RTL code for Low power and multi-clock domain designs.
• Perform synthesis and pre- and post-layout timing closure.
• Run the whole front-end design flow such as Synthesis, power analysis, and normal check etc.
• Contribute test specifications and support evaluation of the design in coordination with application and product engineering.
• Provide design documentation, descriptions and information to application engineers, field application engineers, products engineers, and customers.

• Major in EE, CS or related, Master Degree with 2+ years or Bachelor with 4+ years working experiences in ASIC design.
• Familiar with Verilog and RTL design
• Good problem solving and communication skills
• Good written and spoken English. Be able to work together with global team.
• Familiar with System-Verilog and UVM verification methodology is a plus
• Familiar with script languages (perl, tcl etc.) is a plus
• Familiar with STA timing flow is a plus