129 Digital Ic Design jobs in Singapore

Job Overview

We are seeking an experienced semiconductor digital IC design engineer to join our team. The ideal candidate will have a strong background in ASIC design and development, with expertise in system-on-chip (SoC) timing constraint management, synthesis, and timing closure.

• Work closely with system engineers to ensure timely delivery of projects, providing feedback on optimization opportunities.
• Develop and implement effective power structures, including isolation of power domains and level-shifter crossing voltage domains.
• Conduct formal verification to compare release versions and identify areas for improvement.
• SUPPORT THE BACK-END IMPLEMENTATION TEAM IN TIMING VIOLATION ANALYSIS AND FIXES.
• Support the insertion and optimization of scan elements.
• Collaborate with the power structure team to optimize power consumption.

Requirements

To succeed in this role, you will need:

• A Bachelor's or Master's degree in Electronic Engineering with relevant ASIC design experience.
• Familiarity with the ASIC design flow and tools.
• Strong understanding of logic synthesis, static timing analysis, and timing closure techniques.
• Good knowledge of Design-for-Test (DFT) and power structure principles.
• Experience working in a UNIX/Linux environment and proficiency in scripting languages.
• Excellent communication and interpersonal skills.
• Strong analytical and problem-solving skills.

What We Offer

In addition to a competitive salary and benefits package, we offer a dynamic and supportive work environment that fosters growth and development.

Job Title: Advanced Digital IC Design Specialist

We are seeking an experienced and skilled Digital IC Design Specialist to join our team. The successful candidate will be responsible for designing and developing SerDes IP products, working closely with Physical designers and other teams to achieve timing closure.

The ideal candidate will have a strong background in digital IC design, with experience in Verilog HDL and VHDL RTL design, Logic Synthesis, DFT, ATPG, and Timing Closure. They will also have experience using EDA tools from Cadence and Synopsys.

• Design and develop SerDes IP products
• Perform Logic Synthesis and Static Timing Analysis
• Lead DFT related activities - Scan Insertion, ATPG, Pattern Validation
• Work with Physical designer and RTL designer to achieve timing closure
• Collaborate with test team in debugging production test issues

• Degree or Master in Electrical Electronic Engineering
• 5 years or above experience in the area of digital IC design
• Working experience from design to tape-out is essential
• Experience in Verilog HDL and VHDL RTL design, Logic Synthesis, DFT, ATPG, Timing Closure
• Experience in using EDA tools from Cadence, Synopsys

• Strong Communication skills
• High level of independence, self-motivation, and a good team player

Our team is committed to delivering high-quality designs and solutions, and we are looking for someone who shares our values and can contribute to our success.

JOB DESCRIPTION

• Discussion with system engineers on SoC architecture and feedback on optimization.
• Work on SoC integration; system block development, e.g., power management, clock/reset, system register, test control, PinMux, etc;
• Discussion with synthesis engineer and back-end engineer on design optimization.   
• SoC DFT support;
• SoC verification plan and SoC verification support

JOB REQUIREMENTS

• Bachelor's or Master's Degree in Electronic Engineering with ASIC design experience.
• Knowledge of ASIC design flow
• Experience in RTL coding, RTL and gate-level debug
• Understanding of DFT, timing and power requirements
• Familiar with UNIX/ Linux environment and scripting
• Good communication and interpersonal skills
• Strong analytical and problem-solving skills
• Knowledge on mixed-signal design would be an advantage.

JOB DESCRIPTION

• Discussion with system engineers on IP requirement and micro architecture.
• Develop IP (control path intensive or data path intensive) meet functional requirement and protocol standard.
• Support SoC designer on integration, timing constraints and power domain setting.
• Support IP verification for verification plan review, test case debugging.

JOB REQUIREMENTS

• Bachelor's or Master's Degree in Electronic Engineering with ASIC design experience.
• Experience in IP development (either control path intensive or data path intensive)
• Knowledge of timing, DFT and power structure.
• Familiar with UNIX/ Linux environment and scripting
• Experience on communication IP and/or video IP development would be advantage.
• Good communication and interpersonal skills
• Strong analytical and problem-solving skills
• Experience on communication IP development would be an advantage
• Experience on video IP development would be an advantage

JOB DESCRIPTION

• Work with system engineers on timing requirements and feedback on optimization.  
• Work on SoC timing constraint, synthesis and timing closure.
• Work on power structure, eg. Isolation of power domains, level-shifter crossing voltage domains 
• Conduct formal verification for release comparison.
• Support back-end implementation on timing violation analysis and fix. 
• Support scan insertion and optimization.
• Support on power structure and power optimization.   

JOB REQUIREMENTS

• Bachelor's or Master's Degree in Electronic Engineering with ASIC design experience.
• Familiar with ASIC design flow
• Experience in logic synthesis, static timing analysis, timing closure
• Good understanding of DFT and Power structure.
• Familiar with UNIX/ Linux environment and scripting
• Good communication and interpersonal skills

JOB DESCRIPTION

• Discussion with system engineers on IP requirement and micro architecture.
• Develop IP (control path intensive or data path intensive) meet functional requirement and protocol standard.
• Support SoC designer on integration, timing constraints and power domain setting.
• Support IP verification for verification plan review, test case debugging.

JOB REQUIREMENTS

• Bachelor's or Master's Degree in Electronic Engineering with ASIC design experience.
• Experience in IP development (either control path intensive or data path intensive)
• Knowledge of timing, DFT and power structure.
• Familiar with UNIX/ Linux environment and scripting
• Experience on communication IP and/or video IP development would be advantage.
• Good communication and interpersonal skills
• Strong analytical and problem-solving skills
• Experience on communication IP development would be an advantage
• Experience on video IP development would be an advantage

JOB DESCRIPTION

• Discussion with system engineers on SoC architecture and feedback on optimization.
• Work on SoC integration; system block development, e.g., power management, clock/reset, system register, test control, PinMux, etc;
• Discussion with synthesis engineer and back-end engineer on design optimization.
• SoC DFT support;
• SoC verification plan and SoC verification support

JOB REQUIREMENTS

• Bachelor's or Master's Degree in Electronic Engineering with ASIC design experience.
• Knowledge of ASIC design flow
• Experience in RTL coding, RTL and gate-level debug
• Understanding of DFT, timing and power requirements
• Familiar with UNIX/ Linux environment and scripting
• Good communication and interpersonal skills
• Strong analytical and problem-solving skills
• Knowledge on mixed-signal design would be an advantage.