1,928 Power Management Ics jobs in Singapore

(Are you the right talent?)

• Bachelor's Degree / Master's Degree / PhD in EEE (major in IC Design).

• Knowledge of Switch-mode regulator, LDO, Voltage reference, oscillator, and analog designs through final year project and internship are an added advantage.

• Training will be provided.

(About the team)

MediaTek strives to be a global operation and technology leading company, enabling customer success with most innovative products and services. In MediaTek, we believe technology changes lives and a changed life can change the world. Our team focus on power management integrated circuit design for a variety of customer electronics. Passionate talents who always up for challenges and love innovative culture are welcome to apply

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• Solid understanding and experience in key analog layout considerations such as device matching, parasitic, noise coupling, floor planning, sensitive signal routing, current density and reliability considerations
• Familiar with SPICE simulation tool (e.g., Cadence spectre, Synopsys Custom Compiler, Calibre)

Job Responsibilities:

· Design and implementation of mixed signal CMOS IP. Development cycle including circuit design, simulation, modeling, verification and bench characterization.

· Management products utilizing leading edge sub-micron CMOS technologies, e.g., 5/6nm

· Developing state of the art high speed mixed signal IP products that include op amps, comparators, bandgap, low-drop linear regulator, ADCs, DC-DC converters, and high bit-rate (Gbps) Serdes TX/RX.

Requirements:

· Bachelor or above degree in Microelectronic or Electronic and Information Engineering

· 5 years or above experience in the area of analog design

· Good knowledge in analog IC design in high speed Serdes, e.g., PLL, CDR, CTLE/DFE, TX driver etc.

• Solid understanding and experience in key analog layout considerations such as device matching, parasitic, noise coupling, floor planning, sensitive signal routing, current density and reliability considerations
• Familiar with SPICE simulation tool (e.g., Cadence spectre, Synopsys Custom Compiler, Calibre)

· Strong Communication skills, high level of independence, self-motivation and good team player

What will you be working on:

1.Design one or several of the following high performance analog circuit: high speed and low power ADC, high linearity and low noise amplifier, high linearity and low noise analog filter; high performance PLL, low noise OSC, high speed SERDES, inductive or capacitive base power converter, low noise LDO, high performance temperature sensor, low noise and high accuracy voltage/current reference etc.

1. Plan and perform silicon engineering validation of the responsible analog circuit. Perform silicon debug. Work with test engineer to plan and determine ATE test plan for the responsible analog circuit.

What are we looking for:

1. Bachelor in electrical engineering, Master degree in electrical engineering with 3 years of experience or more, PhD in electrical engineering with 1 years of experience or more.

2. Good experience in some area of analog design in job descriptions.

3. Solid understanding of analog design fundamentals including device physics, analog circuit analysis, sampling theory, control theory and good understanding of communication theory.

4.Strong analytical skill and familiar with underline theory for both time domain analysis and frequency domain analysis

1. Solid understanding and experience in key analog layout considerations such as device matching, parasitic, noise coupling, floor planning, sensitive signal routing, current density and reliability considerations.

2. Familiar with both schematic and layout tool, methodologies, flow and CAD tools such as SPICE, Cadence virtuoso, Spectre, PCELL layout, Calibre physical verification.

3. Good team work, responsible, good communication skill.

4. Suitable candidates with relevant experiences will be considered for a senior role.

Requirements

• Master’s degree and/or PhD Preferred in Electrical Engineering or related fields with 2+ years of experience.
• Should have strong analog design fundamentals and experience in designing analog circuit blocks such as PLL, Data Converters, Oscillators and high-speed SerDes blocks (CTLE, FFE, DFE, CDR, PLL, Line driver, etc.).
• Experience with analog design and verification tools (Virtuoso, Spectre, ADE and post layout extraction tools) is a must
• Knowledge of the fundamentals on signal integrity improvement, noise reduction and Multi-GHz low-jitter clock generation & distribution.
• Good understanding of analog layouts in FinFet and its effect on high-speed designs
• Experienced in system level pre-tape out analog validation
• Experienced in lab chip bring-up and debugging efforts
• Strong communication and documentation skills

Job Responsibilities

• The candidate will be working on analog design of high-speed and high-performance SerDes in advanced technology nodes, 3nm, 2nm and beyond.
• Participate in SerDes Architecture Development with DSP, Analog and Digital design teams.
• Work with the AE for the IP characterization and validation plan
• Product and customer supporting.
• Provide instructions to the layout engineers

Requirements

• Master’s degree and/or PhD Preferred in Electrical Engineering or related fields with 6+ years of experience.
• Should have strong analog design fundamentals and experience in designing analog circuit blocks such as PLL, Data Converters, Oscillators and high-speed SerDes blocks (CTLE, FFE, DFE, CDR, PLL, Line driver, etc.).
• Experience with analog design and verification tools (Virtuoso, Spectre, ADE and post layout extraction tools) is a must
• Knowledge of the fundamentals on signal integrity improvement, noise reduction and Multi-GHz low-jitter clock generation & distribution.
• Good understanding of analog layouts in FinFet and its effect on high-speed designs
• Experienced in system level pre-tape out analog validation
• Experienced in lab chip bring-up and debugging efforts
• Strong communication and documentation skills
• Technical management experience is a plus

Job Responsibilities

• Analog circuit design, such as PLL, Data Converters, Oscillators and high-speed SerDes blocks (CTLE, FFE, DFE, CDR, PLL, Line driver, etc.).
• New technique development for next generation SERDES
• Project leading and management
• Analog layouts supervise with advanced process node
• System verification and circuit design spec creation
• Silicon bring-up, debug and support
• Team communication and documentation

• Seeking an Analog IC Designer to be part of a Marvell's central engineering team designing highly sophisticated CMOS transceiver/SERDES/and essential analog IPs.
• Responsibilities would span architectural investigations and implementation for circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, CDRs etc. to meet key performance targets and performing design verification using industry standard tools such as SPICE, Spectre, MATLAB etc.
• Successful candidate will work on analog design, interface with layout, verification, and application teams and manage delivery of analog IP to successfully bring designs from concept to production.

• Master's degree and/or PhD in Computer Science, Electrical Engineering or related fields with more than 5 years' experience.
• Strong circuit fundamentals and experience in designing some of the circuit blocks such as PLL, Data Converters, Oscillators and high-speed SerDes blocks (CTLE, FFE, DFE, CDR, transmitters etc.), high-speed/low-jitter clocking.
• Experience with analog design and verification tools (Virtuoso, Spectre, ADE and post extraction tools) is a must.
• Excellent problem solving and analytical skills. Experienced in lab chip bring-up and debugging.
• Strong communication and documentation skills.

About the Role:

As a Senior AI Analog Chip Design Engineer, you will be a technical leader, driving the design and optimization of complex analog and mixed-signal circuits for our next-generation AI chips. You will leverage your deep expertise to architect innovative solutions, guide the development of high-performance digital standard cell libraries, and provide strategic direction to layout teams. Your extensive experience will be crucial in ensuring successful tape-outs and fostering a culture of technical excellence within the team.

Responsibilities:

• Lead Analog Innovation: Spearhead the design, simulation, and optimization of sophisticated analog circuits, utilizing advanced tools (Cadence Virtuoso, Spectre, HSPICE) to achieve exceptional performance, power efficiency, and robustness across various operating conditions.
• Drive Digital Library Excellence: Direct the development and characterization of high-performance, low-power digital standard cell libraries, ensuring they meet stringent performance, power, and area targets for AI applications.
• Architect Advanced Cell Solutions: Conceive and implement novel digital standard cell architectures and methodologies to enhance design productivity and address the unique demands of AI workloads.
• Provide Layout Vision: Offer strategic guidance and oversight to layout engineers, ensuring accurate and efficient physical implementations that meet critical performance and reliability specifications in deep sub-micron technologies.
• Technical Leadership & Mentorship: Lead cross-functional teams, mentor junior and mid-level engineers, and promote a collaborative and innovative environment.
• Communication & Collaboration: Effectively communicate complex technical concepts to diverse audiences and collaborate seamlessly with digital design, architecture, and verification teams.
• Tape-Out Ownership: Take ownership of analog and mixed-signal blocks through the entire tape-out process, ensuring successful delivery.

Qualifications:

• Education: Bachelor's degree in Electronics Engineering, Computer Science, or a related field. Master's or Ph.D. strongly preferred.
• Experience: Minimally 8-12+ years of progressive and in-depth experience in analog circuit design and digital standard cell development, with a strong track record in deep sub-micron process technologies (12nm and below). Proven leadership in tape-out of complex analog blocks is essential.
• Technical Mastery: Deep and proven expertise in advanced analog design techniques, power optimization strategies, and thorough noise analysis.
• Tool Proficiency: Mastery-level proficiency in industry-standard EDA tools such as Cadence Virtuoso, Spectre, and HSPICE for schematic capture, simulation, and analysis.
• Digital Cell Expertise: Extensive experience in the complete lifecycle of digital standard cell library creation, characterization, and optimization for power, performance, and area.
• Deep Sub-Micron Knowledge: Comprehensive understanding of the challenges associated with deep sub-micron design, including advanced layout optimization techniques, power delivery network design, and signal integrity considerations.
• Leadership & Communication: Demonstrated ability to effectively lead and inspire technical teams, mentor engineers, and possess exceptional written and verbal communication skills.

About the Role

As a Senior AI Analog Chip Design Engineer, you will be a technical leader, driving the design and optimization of complex analog and mixed-signal circuits for our next-generation AI chips. You will leverage your deep expertise to architect innovative solutions, guide the development of high-performance digital standard cell libraries, and provide strategic direction to layout teams. Your extensive experience will be crucial in ensuring successful tape-outs and fostering a culture of technical excellence within the team.

• Lead Analog Innovation: Spearhead the design, simulation, and optimization of sophisticated analog circuits, utilizing advanced tools (Cadence Virtuoso, Spectre, HSPICE) to achieve exceptional performance, power efficiency, and robustness across various operating conditions.
• Drive Digital Library Excellence: Direct the development and characterization of high-performance, low-power digital standard cell libraries, ensuring they meet stringent performance, power, and area targets for AI applications.
• Architect Advanced Cell Solutions: Conceive and implement novel digital standard cell architectures and methodologies to enhance design productivity and address the unique demands of AI workloads.
• Provide Layout Vision: Offer strategic guidance and oversight to layout engineers, ensuring accurate and efficient physical implementations that meet critical performance and reliability specifications in deep sub-micron technologies.
• Technical Leadership & Mentorship: Lead cross-functional teams, mentor junior and mid-level engineers, and promote a collaborative and innovative environment.
• Communication & Collaboration: Effectively communicate complex technical concepts to diverse audiences and collaborate seamlessly with digital design, architecture, and verification teams.
• Tape-Out Ownership: Take ownership of analog and mixed-signal blocks through the entire tape-out process, ensuring successful delivery.

• Education: Bachelor’s degree in Electronics Engineering, Computer Science, or a related field. Master’s or Ph.D. strongly preferred.
• Experience: Minimally 8-12+ years of progressive and in-depth experience in analog circuit design and digital standard cell development, with a strong track record in deep sub-micron process technologies (12nm and below). Proven leadership in tape-out of complex analog blocks is essential.
• Technical Mastery: Deep and proven expertise in advanced analog design techniques, power optimization strategies, and thorough noise analysis.
• Tool Proficiency: Mastery-level proficiency in industry-standard EDA tools such as Cadence Virtuoso, Spectre, and HSPICE for schematic capture, simulation, and analysis.
• Digital Cell Expertise: Extensive experience in the complete lifecycle of digital standard cell library creation, characterization, and optimization for power, performance, and area.
• Deep Sub-Micron Knowledge: Comprehensive understanding of the challenges associated with deep sub-micron design, including advanced layout optimization techniques, power delivery network design, and signal integrity considerations.
• Leadership & Communication: Demonstrated ability to effectively lead and inspire technical teams, mentor engineers, and possess exceptional written and verbal communication skills.