701 Verification jobs in Singapore

About Our Employer

We are a global leader in the development and design verification of ultra-low power semiconductor solutions. We play a significant role in research, development, and design verification of advanced microcontrollers (MCUs) and system-on-chip (SoC) products.

We collaborate closely with international counterparts and regional customers to ensure high-quality, energy-efficient designs and swift integration of products into various applications.

We foster a culture of innovation, collaboration, and continuous professional growth, contributing significantly to our mission of advancing sustainable, low-power technology solutions.

Key Responsibilities:

• Develop detailed verification plans based on design specifications and architectural requirements.
• Create and maintain testbenches for complex digital designs using SystemVerilog and UVM (Universal Verification Methodology).
• Write, debug, and execute test cases to verify functionality, performance, and power consumption of our SoC and MCU products.
• Collaborate with design engineers to identify, analyze, and resolve design issues.
• Conduct coverage analysis and drive verification closure to ensure all functional requirements are met.
• Mentor junior verification engineers, providing technical guidance and support.
• Continuously improve verification processes and methodologies to enhance efficiency and effectiveness.
• Participate in design and verification reviews, providing constructive feedback and recommendations.
• Stay updated with the latest industry trends and advancements in verification techniques and tools.

Required Skills and Qualifications:

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• At least 7 years of experience at block/sub-system/full-chip verification level.
• Proficiency in SystemVerilog, C/C++, Python, Makefile, with a strong understanding of digital design principles.
• Experience with simulation tools such as VCS, ModelSim, or equivalent.
• Strong analytical and problem-solving skills, with a keen attention to detail.
• Excellent communication and teamwork skills, with the ability to collaborate effectively in a cross-functional environment.
• Demonstrated ability to manage multiple tasks and projects, prioritizing effectively to meet deadlines.
• Knowledge of low-power design techniques and verification methodologies is a plus.

Job Title: Design Verification Manager

We are seeking an experienced and highly skilled Design Verification Manager to lead our passionate verification team in developing and deploying state-of-the-art verification methodologies.

• Verification Team Leadership: Manage a team of skilled engineers responsible for verifying complex digital designs with precision and efficiency.
• Methodology Development: Develop and deploy advanced verification methodologies using UVM, C/C++ co-simulation, system emulation, mixed-mode simulation, and formal verification techniques.
• Test Plan Execution: Conduct thorough test plan reviews and execute plans on-time with high quality results, ensuring defect-free outcomes.

• SoC Design Expertise: Strong knowledge of System-on-Chip (SoC) design principles, including IP block integration and system-level verification practices.
• Test Planning Experience: Experience with test plan development, execution, and analysis, with a focus on quality and efficiency.
• EDA Tools Familiarity: Familiarity with Electronic Design Automation (EDA) tools and development flows for ASIC verification, including UVM.
• Leadership Skills: Highly disciplined, quality-minded, and highly driven for excellence, with excellent team leadership and communication skills.
• UVM Verification Methodology: Strong expertise in Universal Verification Methodology (UVM) verification methodology, including its application and implementation.
• Programming Skills: Experience in C and/or a scripting language such as Python or Perl, with a focus on automation and tool development.
• Education: Master's degree in Electrical Engineering or Computer Engineering, with at least 10 years of relevant experience in the field of verification and testing.
• Bonus Requirements: Experience in RTL design, video processing, and video analytics is a plus, offering additional skills and expertise to the role.

This role requires a strong technical leader who can drive innovation and excellence in verification methodologies, leading to improved productivity and quality outcomes. If you have a passion for leading a talented team and driving cutting-edge technology, we encourage you to apply.

• Develop verification platforms and test cases using SystemVerilog and UVM based on verification plans.
• Promote and implement Formal Property Verification (FPV) for relevant design modules.
• Perform RTL and gate-level simulation, execute regression tests, and debug failures.
• Analyze code and functional coverage to identify and close coverage gaps.
• Contribute ideas and improvements to enhance verification methodologies and processes.

• Education: Master's or PhD degree in Electrical Engineering, Computer Engineering, Computer Science, or related fields.
• Experience: Internship or project experience in chip design/verification preferred. Open to fresh graduates with relevant coursework or research experience.
• Programming Skills: Proficiency in SystemVerilog and scripting languages such as Python, Perl, or Shell.
• Problem-Solving: Strong analytical and debugging skills; ability to work through complex technical challenges.
• Teamwork: Collaborative mindset with strong communication skills and willingness to learn in a fast-paced team environment.

Job Overview

We are seeking a highly skilled Design Verification Engineer to join our team. This is an exciting opportunity to work on next-generation automotive SoCs and develop industry-grade verification platforms and methodologies.

Key Responsibilities:

• Develop verification platforms and test cases using SystemVerilog and UVM based on verification plans.
• Promote and implement Formal Property Verification (FPV) for relevant design modules.
• Perform RTL and gate-level simulation, execute regression tests, and debug failures.
• Analyze code and functional coverage to identify and close coverage gaps.
• Contribute ideas and improvements to enhance verification methodologies and processes.

Qualifications/Requirements:

• Educational Background: Master's or PhD degree in Electrical Engineering, Computer Engineering, Computer Science, or related fields.
• Experience: Internship or project experience in chip design/verification preferred. Open to fresh graduates with relevant coursework or research experience.
• Programming Skills: Proficiency in SystemVerilog and scripting languages such as Python, Perl, or Shell.
• Problem-Solving: Strong analytical and debugging skills; ability to work through complex technical challenges.
• Teamwork: Collaborative mindset with strong communication skills and willingness to learn in a fast-paced team environment.

• Develop detailed module level and SoC level testplans for all the functional features, based on the design spec.
• Develop ASIC verification environment including all the respective components such as stimulus, checkers, assertions, monitors and scoreboards.
• Develop directed and constrain-random verification functional tests, and simulate using EDA tools to verify functional blocks is working.
• Execute verification plans, including design bring-up, DV bring-up, regression enabling for all the features.
• Collaborate with design team to debug functional testcases and deliver functionally correct designs.

As a Design Verification Manager, you are expected to carry out the following responsibilities.

• Be in-charge of a passionate verification team that is constantly pushing the limits
• Developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode simulation & formal verification.
• Conduct thorough test plan reviews systematically and execute the plan on-time with high quality.
• Achieve zero-defect, with the best and smartest approach to the large verification space.

Requirements

• Strong knowledge of SoC design principles, including IP block integration and system-level verification
• Experience with test plan development, execution, and analysis
• Familiarity with EDA tools and development flows for ASIC verification
• Highly disciplined, quality-minded, and highly driven for excellence.
• Excellent team leader and good communication skills.
• Strong expertise in UVM verification methodology.
• Experience in C and/or a scripting language such as python or perl.
• MSEE/BSEE in Electrical Engineering or Computer Engineering, with at least 10 years of relevant experience.
• Experience in RTL design is a plus.
• Experience in video processing and video analytics is a plus.
• Passionate and strong in general programming is a plus.

As a Design Verification Manager, you are expected to carry out the following responsibilities.

• Be in-charge of a passionate verification team that is constantly pushing the limits – developing and deploying state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode simulation & formal verification.
• Conduct thorough test plan reviews systematically and execute the plan on-time with high quality.
• Achieve zero-defect with the best and smartest approach to the large verification space.

Requirements

• Strong knowledge of SoC design principles, including IP block integration and system-level verification
• Experience with test plan development, execution, and analysis
• Familiarity with EDA tools and development flows for ASIC verification
• Highly disciplined, quality-minded, and highly driven for excellence.
• Excellent team leader and good communication skills.
• Strong expertise in UVM verification methodology.
• Experience in C and/or a scripting language such as python or perl.
• MSEE/BSEE in Electrical Engineering or Computer Engineering, with at least 10 years of relevant experience.
• Experience in RTL design is a plus.
• Experience in video processing and video analytics is a plus.
• Passionate and strong in general programming is a plus.

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Description

As a Design Verification Manager, you are expected to carry out the following responsibilities.

• Be in-charge of a passionate verification team that is constantly pushing the limits
• Develop and deploy state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode simulation & formal verification
• Conduct thorough test plan reviews systematically, and execute the plan on-time with high quality
• Achieve zero-defects with the best and smartest approach to the large verification space.
  
  

• Be in-charge of a passionate verification team that is constantly pushing the limits
• Develop and deploy state-of-the-art verification methodologies in ever-increasing design complexities, from UVM, C/C++ co-simulation, system emulation to mixed-mode simulation & formal verification
• Conduct thorough test plan reviews systematically, and execute the plan on-time with high quality
• Achieve zero-defects with the best and smartest approach to the large verification space.
  
  

• Strong knowledge of SoC design principles, including IP block integration and system-level verification
• Experience with test plan development, execution, and analysis
• Familiarity with EDA tools and development flows for ASIC verification
• Highly disciplined, quality-minded, and highly driven for excellence.
• Excellent team leader and good communication skills.
• Strong expertise in UVM verification methodology.
• Experience in C and/or a scripting language such as python or perl.
• MSEE/BSEE in Electrical Engineering or Computer Engineering, with at least 10 years of relevant experience.
• Experience in RTL design is a plus.
• Experience in video processing and video analytics is a plus.
• Passionate and strong in general programming is a plus.

• Seniority level Mid-Senior level

• Employment type Full-time

• Job function Quality Assurance
• Industries Semiconductor Manufacturing

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• Develop verification platforms and test cases using SystemVerilog and UVM based on verification plans.
• Promote and implement Formal Property Verification (FPV) for relevant design modules.
• Perform RTL and gate-level simulation, execute regression tests, and debug failures.
• Analyze code and functional coverage to identify and close coverage gaps.
• Contribute ideas and improvements to enhance verification methodologies and processes.

• Education: Master's or PhD degree in Electrical Engineering, Computer Engineering, Computer Science, or related fields.
• Experience: Internship or project experience in chip design/verification preferred. Open to fresh graduates with relevant coursework or research experience.
• Programming Skills: Proficiency in SystemVerilog and scripting languages such as Python, Perl, or Shell.
• Problem-Solving: Strong analytical and debugging skills; ability to work through complex technical challenges.
• Teamwork: Collaborative mindset with strong communication skills and willingness to learn in a fast-paced team environment.