958 Verification Engineer jobs in Singapore

Key Responsibilities:

• Develop and implement comprehensive verification plans for IP and SoC levels.
• Architect and build reusable testbenches and verification environments using UVM (Universal Verification Methodology).
• Create directed and constrained-random tests to identify design bugs.
• Develop functional coverage and assertion checks to ensure verification completeness.
• Analyze simulation results, debug test failures, and work with design teams to resolve issues.
• Automate verification flows and regressions using scripting languages.
• Support emulation and FPGA prototyping efforts.

Qualifications and Skills:

• Bachelor's or Master's degree in Electrical/Electronics Engineering, Computer Science, or a related field.
• Solid experience in functional verification of ASICs/SoCs.
• Strong proficiency in SystemVerilog and UVM methodology.
• Experience with verification tools and simulators (e.g., VCS, Xcelium, Questa).
• Programming and scripting skills (e.g., C/C++, Python, Perl, TCL) are highly desirable.
• Knowledge of formal verification techniques is a plus.
• Strong analytical and debug skills with a keen attention to detail.
• Ability to work effectively in a collaborative, cross-functional team.

Key Responsibilities:

• Develop and implement comprehensive verification plans for IP and SoC levels.
• Architect and build reusable testbenches and verification environments using UVM (Universal Verification Methodology).
• Create directed and constrained-random tests to identify design bugs.
• Develop functional coverage and assertion checks to ensure verification completeness.
• Analyze simulation results, debug test failures, and work with design teams to resolve issues.
• Automate verification flows and regressions using scripting languages.
• Support emulation and FPGA prototyping efforts.

Qualifications and Skills:

• Bachelor's or Master's degree in Electrical/Electronics Engineering, Computer Science, or a related field.
• Solid experience in functional verification of ASICs/SoCs.
• Strong proficiency in SystemVerilog and UVM methodology.
• Experience with verification tools and simulators (e.g., VCS, Xcelium, Questa).
• Programming and scripting skills (e.g., C/C++, Python, Perl, TCL) are highly desirable.
• Knowledge of formal verification techniques is a plus.
• Strong analytical and debug skills with a keen attention to detail.
• Ability to work effectively in a collaborative, cross-functional team.

One of our US Global Semiconductor IC design is growing their design teams in Singapore.

Role : Design Verification Engineer (DV)

Location : Singapore

Experience : 3 to 7 years.

• Technical Requirements:

o Expert-level UVM and SystemVerilog verification

o Advanced coverage-driven verification methodologies

o Experience with complex SoC verification strategies

o Knowledge of ARM CPU verification techniques

o Understanding of high-speed interface verification (PCIe, USB, DDR)

o Formal verification and assertion-based verification

o Verification planning and test strategy development

o Team leadership and mentoring capabilities

• Key Responsibilities:

o Overall verification strategy and planning

o Test plan development and review

o Coverage goals and sign-off criteria definition

o Verification environment architecture

o Team coordination and quality oversight

o Final verification sign-off

EA licence : 14C7174

Our Purpose

TERADYNE, where experience meets innovation and driving excellence in every connection.

We are fueled by creativity and diversity of thought and in our workforce. Our employees are supported to innovate and learn something new every day.

We cultivate a culture of inclusion for all employees that respects their individual strengths, views, and experiences. We believe that our differences enable us to be a better team – one that makes better decisions, drives innovation and delivers better business results.

Opportunity Overview

The Quality Engineering (QE) Team is responsible for assessing quality at all states of the Software Development Life Cycle so that Teradyne maintains its quality leadership in the Automated Test Equipment (ATE) industry.

The Software Verification/Quality Engineer is an integral member of the QE team, using and developing automated tests for Teradyne's flagship software products, as well as working with various in-house tools and industry leading digital and analog hardware.

The Teradyne Quality Engineering team is looking for a highly motivated, energetic, software engineer who will work collaboratively with the test and development teams as well as independently to determine and develop imaginative, thorough, and practical testing solutions.

This individual is responsible for:

• Reviewing system, hardware, software and user interface requirements documentation
• Planning, designing, creating, executing, and automating tests focused on proving our products meet stringent requirements
• System and user-focused testing that extends beyond the written requirements of the product
• Enhancing in-house tools to make test creation more efficient and effective.
• Managing defects in the defect tracking database to report, track, manage, and resolve issues found during product verification.
• Interacts with software and hardware engineering teams, working closely with Software Development Engineering to prepare and continually manage a test strategy for defect assessment, peer reviews, test coverage analysis, and various levels of system integration tests.

In addition, this engineer will work closely with our Applications teams to:

• Participate in customer account, Teradyne engineering, Applications, and Marketing teams to understand key business and technical requirements.
• Analyze problems and recommend solutions on Teradyne ATE platform to optimize customer throughput and performance
• Work directly with test engineering customers to understand and improve test process; making recommendations to improve quality of test coverage.
• Develop shared knowledge in the form of application solutions and test techniques.
• This position may require some amount of travel %) to customer sites to support beta testing and transition teams.

All About You

We seek individuals who share our passion and determination. Our commitment to customer success drives us to go the extra mile. If you're ready to join us in this mission, take a closer look at the minimum criteria for the position.

• BSEE/BSCS/BS Computer Engineering/BS Software Engineering or equivalent
• Familiarity with Agile and Waterfall Software Development Life Cycles (SDLC)
• Programming with C/C++, C# and VBA/VB.NET/Excel
• Other experience with scripting languages such as Perl or Python
• Experience using MS Visual Studio, github, JIRA, and other SW Development related tools
• Understanding of embedded systems, digital, power, and/or analog hardware is highly desired
• Experience testing and/or developing test applications for semiconductors
• Comfortable working directly with customers and representing Teradyne's strong commitment to quality.
• Effective written and verbal communications skills in English
• Able to work in an international, multi-site, dynamic and diverse team-oriented environment
• 5+ years of test/product engineering experience in analog, digital and mixed signal testing with strong background in test design and development.
• Any experience with ATE equipment (Teradyne or others) is highly desired

We are only considering candidates local to position location and are unable to provide relocation for this position.

This position is not eligible for visa sponsorship.

Benefits:

Teradyne offers a variety of robust health and well-being benefit programs, including outpatient medical, flexible benefits, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more.

Job Segment:
Test Engineer, Software Engineer, Testing, User Experience, Embedded, Engineering, Technology

• Perform chip verification for new product development.
• Participate in IP- and system-level simulation verification.
• Develop and maintain UVM-based verification environments according to architectural documentation.
• Define and achieve functional coverage targets; improve code and functional coverage based on the verification plan.
• Execute verification across gate-level and post-simulation stages; debug issues, resolve cases, and ensure verification tasks are completed at each project milestone.
• Support validation requirements and contribute to successful tape-out.

• M.S. in Electrical Engineering, Microelectronics, or related field.
• 5+ years of experience in Pre-Silicon verification.
• Solid knowledge of UVM methodology (strong advantage).
• Proficiency in Verilog/System Verilog.
• Strong scripting skills in at least one language: Python, Perl, Tcl, or Shell (required).
• Experience with chip CP/FT test preferred.
• Leadership or management experience is a plus.

• Develop and Review Test Plan based on IC design specification
• Develop constrained-Random verification environment for complex DUT
• Implement coverage matrix using cover point and assertion
• Create and debug tests for DUT

• Bachelor/Masters Degree in Electrical/Electronics/Computer Engineering with min 1 year of experience
• Hands-on experience in Silicon/ IP verification using SystemVerilog/UVM
• Strong understanding of verification process from test plan to coverage completion
• Strong communication and Analytical skills
• Understanding of HDL (Verilog, VHDL)

• Develop and implement comprehensive verification plans for IP and SoC levels.
• Architect and build reusable testbenches and verification environments using UVM (Universal Verification Methodology).
• Create directed and constrained-random tests to identify design bugs.
• Develop functional coverage and assertion checks to ensure verification completeness.
• Analyze simulation results, debug test failures, and work with design teams to resolve issues.
• Automate verification flows and regressions using scripting languages.
• Support emulation and FPGA prototyping efforts.

• Bachelor's or Master's degree in Electrical/Electronics Engineering, Computer Science, or a related field.
• Solid experience in functional verification of ASICs/SoCs.
• Strong proficiency in SystemVerilog and UVM methodology.
• Experience with verification tools and simulators (e.g., VCS, Xcelium, Questa).
• Programming and scripting skills (e.g., C/C++, Python, Perl, TCL) are highly desirable.
• Knowledge of formal verification techniques is a plus.
• Strong analytical and debug skills with a keen attention to detail.
• Ability to work effectively in a collaborative, cross-functional team.

One of our US Global Semiconductor IC design is growing their design teams in Singapore.

Role : Design Verification Engineer (DV)

Location : Singapore

Experience : 3 to 7 years.

· Technical Requirements:

o Expert-level UVM and SystemVerilog verification

o Advanced coverage-driven verification methodologies

o Experience with complex SoC verification strategies

o Knowledge of ARM CPU verification techniques

o Understanding of high-speed interface verification (PCIe, USB, DDR)

o Formal verification and assertion-based verification

o Verification planning and test strategy development

o Team leadership and mentoring capabilities

· Key Responsibilities:

o Overall verification strategy and planning

o Test plan development and review

o Coverage goals and sign-off criteria definition

o Verification environment architecture

o Team coordination and quality oversight

o Final verification sign-off

EA licence : 14C7174