1,567 Chip Design jobs in Singapore

Job Summary:

We are seeking an experienced and highly skilled Senior AI Chip Architecture Engineer to lead the development and optimization of cutting-edge AI chip hardware systems. This role requires a strategic thinker with at least 8 years of experience in digital circuit design or chip architecture engineering. The ideal candidate will play a pivotal role in defining chip architecture, designing simulators, optimizing performance at various levels, and driving innovation in AI hardware solutions.

Key Responsibilities:

• AI Chip Architecture Design: Lead the design and development of advanced AI chip architectures to meet performance, power, and efficiency targets.

Define system requirements and architecture strategies for AI accelerators and compute engines.
- Performance Optimization:

Drive optimization efforts at multiple levels: Algorithm Level: Refine computational algorithms to maximize performance.

Architecture Level: Innovate on architecture solutions for scalability and efficiency.

Circuit Level: Enhance electrical performance and address signal integrity issues.
- Simulator Development: Develop, implement, and refine AI chip simulators using tools like GEM5 or custom frameworks.

Analyze simulator outputs and apply insights to architectural decisions.
- Technical Leadership: Mentor and guide junior engineers and collaborate cross-functionally with hardware, software, and R&D teams.

Stay updated with emerging technologies and industry trends to drive innovation.
- Front-End Development: Write, test, and optimize RTL and front-end design code to ensure robust chip functionality and performance.

Qualifications:

• Education: Bachelor's, Master's, or Ph.D. in Computer Science, Electrical/Electronics Engineering, or a related field.
• Experience: 8+ years of hands-on experience in digital circuit design, chip architecture engineering, or AI hardware development.

Proven track record in leading complex architecture design projects and delivering successful chip products.
- Technical Expertise: Deep understanding of computer architecture and AI hardware accelerators (e.g., GPUs, TPUs).

Expertise in memory systems, interconnect design, and optimization of memory access patterns for AI models.

Proficiency in simulation tools (e.g., GEM5) and front-end design languages (e.g., Verilog, VHDL, SystemVerilog).

Strong problem-solving skills with a focus on performance, power, and area (PPA) trade-offs.

Job Overview:

We are seeking a motivated and detail-oriented Junior Physical Chip Design Engineer to contribute to the development of low-power, high-performance chip designs. This role will involve learning and assisting in full-chip physical design workflows, including floor planning, place-and-route, power network design, and physical verification, under the guidance of senior engineers. The ideal candidate will have a foundational understanding of semiconductor technologies and a strong interest in the physical implementation of complex integrated circuits.

Key Responsibilities:

• Assist in the optimization of low-power physical design processes.
• Support full-chip floor planning activities to achieve performance, power, and area targets.
• Learn and apply place-and-route methodologies under supervision.
• Contribute to the design and analysis of power distribution networks.
• Participate in timing closure, power integrity, and signal integrity analysis with guidance from senior team members.
• Develop and utilize scripting skills (e.g., Perl, TCL, Python) for automation.

Qualifications:

• Bachelor's degree or higher in Electronics, Electrical Engineering, Computer Science, or a related field.
• Basic understanding of physical design concepts, floor planning, and place-and-route.
• Familiarity with power distribution and timing concepts is a plus.
• Exposure to physical verification (DRC/LVS) principles.
• Basic scripting skills in Perl, TCL, or Python.
• Strong analytical and problem-solving skills.
• Good communication and teamwork abilities.

About the Role:

As a Senior AI Analog Chip Design Engineer, you will be a technical leader, driving the design and optimization of complex analog and mixed-signal circuits for our next-generation AI chips. You will leverage your deep expertise to architect innovative solutions, guide the development of high-performance digital standard cell libraries, and provide strategic direction to layout teams. Your extensive experience will be crucial in ensuring successful tape-outs and fostering a culture of technical excellence within the team.

Responsibilities:

• Lead Analog Innovation: Spearhead the design, simulation, and optimization of sophisticated analog circuits, utilizing advanced tools (Cadence Virtuoso, Spectre, HSPICE) to achieve exceptional performance, power efficiency, and robustness across various operating conditions.
• Drive Digital Library Excellence: Direct the development and characterization of high-performance, low-power digital standard cell libraries, ensuring they meet stringent performance, power, and area targets for AI applications.
• Architect Advanced Cell Solutions: Conceive and implement novel digital standard cell architectures and methodologies to enhance design productivity and address the unique demands of AI workloads.
• Provide Layout Vision: Offer strategic guidance and oversight to layout engineers, ensuring accurate and efficient physical implementations that meet critical performance and reliability specifications in deep sub-micron technologies.
• Technical Leadership & Mentorship: Lead cross-functional teams, mentor junior and mid-level engineers, and promote a collaborative and innovative environment.
• Communication & Collaboration: Effectively communicate complex technical concepts to diverse audiences and collaborate seamlessly with digital design, architecture, and verification teams.
• Tape-Out Ownership: Take ownership of analog and mixed-signal blocks through the entire tape-out process, ensuring successful delivery.

Qualifications:

• Education: Bachelor's degree in Electronics Engineering, Computer Science, or a related field. Master's or Ph.D. strongly preferred.
• Experience: Minimally 8-12+ years of progressive and in-depth experience in analog circuit design and digital standard cell development, with a strong track record in deep sub-micron process technologies (12nm and below). Proven leadership in tape-out of complex analog blocks is essential.
• Technical Mastery: Deep and proven expertise in advanced analog design techniques, power optimization strategies, and thorough noise analysis.
• Tool Proficiency: Mastery-level proficiency in industry-standard EDA tools such as Cadence Virtuoso, Spectre, and HSPICE for schematic capture, simulation, and analysis.
• Digital Cell Expertise: Extensive experience in the complete lifecycle of digital standard cell library creation, characterization, and optimization for power, performance, and area.
• Deep Sub-Micron Knowledge: Comprehensive understanding of the challenges associated with deep sub-micron design, including advanced layout optimization techniques, power delivery network design, and signal integrity considerations.
• Leadership & Communication: Demonstrated ability to effectively lead and inspire technical teams, mentor engineers, and possess exceptional written and verbal communication skills.

About the Role:

As a Junior AI Analog Chip Design Engineer, you will contribute to the design and development of analog and mixed-signal circuits for our innovative AI chips. You will work closely with senior engineers, gaining hands-on experience in all aspects of the design flow, from specification to layout. This is an excellent opportunity to leverage your foundational knowledge and grow your expertise within a dynamic team focused on pushing the boundaries of AI hardware.

Responsibilities:

• Assist in Analog Circuit Design: Support the design, simulation, and optimization of analog circuits under the guidance of senior engineers, utilizing schematic capture and simulation tools (e.g., Cadence Virtuoso, Spectre, HSPICE).
• Contribute to Digital Standard Cell Development: Assist in the creation and characterization of digital standard cell libraries, learning about performance, power, and area optimization techniques.
• Implement Cell Architectures: Work on the implementation and analysis of digital standard cell architectures, contributing to design efficiency.
• Support Layout Implementation: Collaborate with layout teams to ensure accurate and efficient physical implementations, adhering to performance and reliability guidelines.
• Learn and Apply Advanced Techniques: Develop your understanding of analog design principles, power optimization methods, and noise analysis techniques.
• Utilize Design Tools: Gain proficiency in industry-standard EDA tools such as Cadence Virtuoso, Spectre, and HSPICE.
• Collaborate within the Team: Work effectively within a cross-functional team, communicating progress and challenges clearly.
• Contribute to Tape-Out Preparation: Assist senior engineers in the preparation and review of design data for tape-out.

Qualifications:

• Education: Bachelor's degree in Electronics Engineering, Computer Science, or a related field.
• Experience: Minimally 5-7+ years of relevant experience in analog design and digital standard cell development (including internships and academic projects). A solid understanding of deep sub-micron process technologies is expected.
• Foundational Technical Skills: Strong understanding of fundamental analog design principles, power optimization concepts, and noise fundamentals.
• Tool Familiarity: Proficiency in schematic capture and simulation tools such as Cadence Virtuoso, Spectre, or HSPICE.
• Basic Digital Design Concepts: Understanding of basic digital logic and standard cell concepts.
• Problem-Solving Skills: Strong analytical and problem-solving abilities.
• Communication and Teamwork: Good communication skills and the ability to work effectively in a team environment.
• Eagerness to Learn: A continued strong desire to learn and advance in the field of AI analog chip design.

About the Role:

As a Senior AI Analog Chip Design Engineer, you will be a technical leader, driving the design and optimization of complex analog and mixed-signal circuits for our next-generation AI chips. You will leverage your deep expertise to architect innovative solutions, guide the development of high-performance digital standard cell libraries, and provide strategic direction to layout teams. Your extensive experience will be crucial in ensuring successful tape-outs and fostering a culture of technical excellence within the team.

Responsibilities:

• Lead Analog Innovation: Spearhead the design, simulation, and optimization of sophisticated analog circuits, utilizing advanced tools (Cadence Virtuoso, Spectre, HSPICE) to achieve exceptional performance, power efficiency, and robustness across various operating conditions.
• Drive Digital Library Excellence: Direct the development and characterization of high-performance, low-power digital standard cell libraries, ensuring they meet stringent performance, power, and area targets for AI applications.
• Architect Advanced Cell Solutions: Conceive and implement novel digital standard cell architectures and methodologies to enhance design productivity and address the unique demands of AI workloads.
• Provide Layout Vision: Offer strategic guidance and oversight to layout engineers, ensuring accurate and efficient physical implementations that meet critical performance and reliability specifications in deep sub-micron technologies.
• Technical Leadership & Mentorship: Lead cross-functional teams, mentor junior and mid-level engineers, and promote a collaborative and innovative environment.
• Communication & Collaboration: Effectively communicate complex technical concepts to diverse audiences and collaborate seamlessly with digital design, architecture, and verification teams.
• Tape-Out Ownership: Take ownership of analog and mixed-signal blocks through the entire tape-out process, ensuring successful delivery.

Qualifications:

• Education: Bachelor's degree in Electronics Engineering, Computer Science, or a related field. Master's or Ph.D. strongly preferred.
• Experience: Minimally 8-12+ years of progressive and in-depth experience in analog circuit design and digital standard cell development, with a strong track record in deep sub-micron process technologies (12nm and below). Proven leadership in tape-out of complex analog blocks is essential.
• Technical Mastery: Deep and proven expertise in advanced analog design techniques, power optimization strategies, and thorough noise analysis.
• Tool Proficiency: Mastery-level proficiency in industry-standard EDA tools such as Cadence Virtuoso, Spectre, and HSPICE for schematic capture, simulation, and analysis.
• Digital Cell Expertise: Extensive experience in the complete lifecycle of digital standard cell library creation, characterization, and optimization for power, performance, and area.
• Deep Sub-Micron Knowledge: Comprehensive understanding of the challenges associated with deep sub-micron design, including advanced layout optimization techniques, power delivery network design, and signal integrity considerations.
• Leadership & Communication: Demonstrated ability to effectively lead and inspire technical teams, mentor engineers, and possess exceptional written and verbal communication skills.

Job Overview:

We are seeking a highly skilled and experienced Senior Physical Chip Design Engineer to lead the development and optimization of low-power, high-performance chip design processes. This role requires a deep understanding of advanced semiconductor technologies and the proven ability to oversee full-chip physical design workflows from floor planning to signoff. The ideal candidate will be responsible for driving innovation in power efficiency and performance while ensuring the successful tape-out of complex integrated circuits.

Key Responsibilities:

• Lead the development and optimization of low-power physical design workflows to enhance energy efficiency.
• Oversee full-chip floor planning and place-and-route management to ensure optimal performance, power, and area utilization.
• Architect and optimize power distribution networks to maintain power integrity and minimize losses, conducting thorough power grid analysis.
• Drive timing closure efforts, collaborating with cross-functional teams to meet challenging performance targets.
• Take ownership of power integrity and signal integrity signoff, performing necessary analysis and optimizations.
• Lead comprehensive design rule checks (DRC) and layout versus schematic (LVS) verifications to ensure design compliance and correctness.
• Utilize and optimize industry-standard physical design tools such as Synopsys IC Compiler, Cadence Innovus, or equivalent.
• Leverage strong scripting and programming skills (Perl, TCL, Python, C++) to automate tasks and improve design efficiency.
• Mentor and provide technical guidance to junior physical design engineers.

Qualifications:

• Bachelor's degree or higher in Electronics, Electrical Engineering, Computer Science, or a related field. Advanced degrees (Master's or Ph.D.) are advantageous.
• Minimum 7-8 years of hands-on experience in full-chip physical design with a strong focus on low-power and high-performance chip design.
• Proven experience with advanced semiconductor technologies (12nm and below) and successful tape-out processes.
• Strong expertise in full-chip floor planning, place-and-route methodologies, and physical verification (DRC and LVS).
• In-depth knowledge of power network design, IR drop analysis, and timing closure principles and methodologies.
• Proficiency in using industry-standard physical design tools such as Synopsys IC Compiler, Cadence Innovus, or equivalent.
• Hands-on experience with Static Timing Analysis (STA) tools.
• Proficient in scripting and programming languages, including Perl, TCL, Python, and C++.
• Strong problem-solving skills, attention to detail, and excellent communication and leadership abilities.

Job Overview:

We are seeking a motivated and detail-oriented Junior Physical Chip Design Engineer to contribute to the development of low-power, high-performance chip designs. This role will involve learning and assisting in full-chip physical design workflows, including floor planning, place-and-route, power network design, and physical verification, under the guidance of senior engineers. The ideal candidate will have a foundational understanding of semiconductor technologies and a strong interest in the physical implementation of complex integrated circuits.

Key Responsibilities:

• Assist in the optimization of low-power physical design processes.
• Support full-chip floor planning activities to achieve performance, power, and area targets.
• Learn and apply place-and-route methodologies under supervision.
• Contribute to the design and analysis of power distribution networks.
• Participate in timing closure, power integrity, and signal integrity analysis with guidance from senior team members.
• Develop and utilize scripting skills (e.g., Perl, TCL, Python) for automation.

Qualifications:

• Bachelor's degree or higher in Electronics, Electrical Engineering, Computer Science, or a related field.
• Basic understanding of physical design concepts, floor planning, and place-and-route.
• Familiarity with power distribution and timing concepts is a plus.
• Exposure to physical verification (DRC/LVS) principles.
• Basic scripting skills in Perl, TCL, or Python.
• Strong analytical and problem-solving skills.
• Good communication and teamwork abilities.

About the Role:

As a Junior AI Analog Chip Design Engineer, you will contribute to the design and development of analog and mixed-signal circuits for our innovative AI chips. You will work closely with senior engineers, gaining hands-on experience in all aspects of the design flow, from specification to layout. This is an excellent opportunity to leverage your foundational knowledge and grow your expertise within a dynamic team focused on pushing the boundaries of AI hardware.

Responsibilities:

• Assist in Analog Circuit Design: Support the design, simulation, and optimization of analog circuits under the guidance of senior engineers, utilizing schematic capture and simulation tools (e.g., Cadence Virtuoso, Spectre, HSPICE).
• Contribute to Digital Standard Cell Development: Assist in the creation and characterization of digital standard cell libraries, learning about performance, power, and area optimization techniques.
• Implement Cell Architectures: Work on the implementation and analysis of digital standard cell architectures, contributing to design efficiency.
• Support Layout Implementation: Collaborate with layout teams to ensure accurate and efficient physical implementations, adhering to performance and reliability guidelines.
• Learn and Apply Advanced Techniques: Develop your understanding of analog design principles, power optimization methods, and noise analysis techniques.
• Utilize Design Tools: Gain proficiency in industry-standard EDA tools such as Cadence Virtuoso, Spectre, and HSPICE.
• Collaborate within the Team: Work effectively within a cross-functional team, communicating progress and challenges clearly.
• Contribute to Tape-Out Preparation: Assist senior engineers in the preparation and review of design data for tape-out.

Qualifications:

• Education: Bachelor's degree in Electronics Engineering, Computer Science, or a related field.
• Experience: Minimally 5-7+ years of relevant experience in analog design and digital standard cell development (including internships and academic projects). A solid understanding of deep sub-micron process technologies is expected.
• Foundational Technical Skills: Strong understanding of fundamental analog design principles, power optimization concepts, and noise fundamentals.
• Tool Familiarity: Proficiency in schematic capture and simulation tools such as Cadence Virtuoso, Spectre, or HSPICE.
• Basic Digital Design Concepts: Understanding of basic digital logic and standard cell concepts.
• Problem-Solving Skills: Strong analytical and problem-solving abilities.
• Communication and Teamwork: Good communication skills and the ability to work effectively in a team environment.
• Eagerness to Learn: A continued strong desire to learn and advance in the field of AI analog chip design.

Job Summary:

We are seeking an experienced and highly skilled Senior AI Chip Architecture Engineer to lead the development and optimization of cutting-edge AI chip hardware systems. This role requires a strategic thinker with at least 8 years of experience in digital circuit design or chip architecture engineering. The ideal candidate will play a pivotal role in defining chip architecture, designing simulators, optimizing performance at various levels, and driving innovation in AI hardware solutions.

Key Responsibilities:

• AI Chip Architecture Design:Lead the design and development of advanced AI chip architectures to meet performance, power, and efficiency targets.
  
  Define system requirements and architecture strategies for AI accelerators and compute engines.
  
  
• Performance Optimization:
  
  Drive optimization efforts at multiple levels:Algorithm Level: Refine computational algorithms to maximize performance.
  
  Architecture Level: Innovate on architecture solutions for scalability and efficiency.
  
  Circuit Level: Enhance electrical performance and address signal integrity issues.
  
  
• Simulator Development:Develop, implement, and refine AI chip simulators using tools like GEM5 or custom frameworks.
  
  Analyze simulator outputs and apply insights to architectural decisions.
  
  
• Technical Leadership:Mentor and guide junior engineers and collaborate cross-functionally with hardware, software, and R&D teams.
  
  Stay updated with emerging technologies and industry trends to drive innovation.
  
  
• Front-End Development:Write, test, and optimize RTL and front-end design code to ensure robust chip functionality and performance.
  
  

Qualifications:

• Education: Bachelor's, Master's, or Ph.D. in Computer Science, Electrical/Electronics Engineering, or a related field.
  
  
• Experience: 8+ years of hands-on experience in digital circuit design, chip architecture engineering, or AI hardware development.
  
  Proven track record in leading complex architecture design projects and delivering successful chip products.
  
  
• Technical Expertise: Deep understanding of computer architecture and AI hardware accelerators (e.g., GPUs, TPUs).
  
  Expertise in memory systems, interconnect design, and optimization of memory access patterns for AI models.
  
  Proficiency in simulation tools (e.g., GEM5) and front-end design languages (e.g., Verilog, VHDL, SystemVerilog).
  
  Strong problem-solving skills with a focus on performance, power, and area (PPA) trade-offs.