73 Analog Design jobs in Singapore

Responsibilities:

• Collaborate with Senior Engineers for design requirements and specifications.
• Assist in Analog , mixed-signal , and digital IC design .
• Participate in RTL coding and verification for digital ICs.
• Support design verification tasks.
• Conduct circuit simulations and analysis using Cadence, Synopsys, and Mentor Graphics tools .
• Assist layout engineers with floor planning.
• Analyze and debug silicon failures, suggesting design improvements.
• Contribute to the development of design methodologies to enhance efficiency.
• Document design work and test plans.
• Collaborate with cross-functional teams to ensure successful tape-out.

Requirements:

• Bachelor’s Degree in Electrical Engineering or equivalents.
• At least 2 years of relevant working experience.
• Understanding the IC development flow in advanced CMOS processes, including design, layout, and tape-out.
• Understanding the fundamental theories of digital or analog circuit design.
• Capability to generate inventive designs and circuit solutions tailored to fulfill customer needs.

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Wee Wai Dan

EA License No : 03C5391

EA Reg No : R22109628

Lead Analog Circuit Design Specialist
Job Overview

This position involves the development of advanced analog circuit designs, specifically focusing on DDR or PLL design. The ideal candidate will possess a Master's degree in Electrical Engineering and have at least 5 years of experience in designing complex analog circuits.

• The lead designer will be responsible for spearheading the development of analog circuits, collaborating closely with cross-functional teams to ensure timely completion of projects.

• Support will be provided for mass production and debugging of assigned circuits.

• Cross-functional participation is expected in the development of other SerDes-related IPs, including task coordination related to product integration.

• A minimum Master's degree in Electrical Engineering, Microelectronics, or a related field; minimum 5 years of experience in analog circuit design.

• At least 3 years of hands-on experience specializing in DDR or PLL design, demonstrating the ability to work independently and having substantial tape-out experience.

• Experience with FINFET processes is an added advantage.

• Possessing proactive, detail-oriented, and responsible traits, with strong communication skills, and a positive work attitude as well as a collaborative mindset.

• Tape Modeling
• Analog Architecture Design
• Analog Circuit Design
• Good Communication Skills
• IP Development
• CMOS Design
• Architecture Design
• Analog Design
• Team Player
• Debugging

We are seeking an experienced Analog Design Engineer to join our team in Singapore.

Job Responsibilities:

· Design and implementation of mixed signal CMOS IP. Development cycle including circuit design, simulation, modeling, verification and bench characterization.

· Management products utilizing leading edge sub-micron CMOS technologies, e.g., 5/6nm

· Developing state of the art high speed mixed signal IP products that include op amps, comparators, bandgap, low-drop linear regulator, ADCs, DC-DC converters, and high bit-rate (Gbps) Serdes TX/RX.

Requirements:

· Bachelor or above degree in Microelectronic or Electronic and Information Engineering

· 5 years or above experience in the area of analog design

· Good knowledge in analog IC design in high speed Serdes, e.g., PLL, CDR, CTLE/DFE, TX driver etc.

• Solid understanding and experience in key analog layout considerations such as device matching, parasitic, noise coupling, floor planning, sensitive signal routing, current density and reliability considerations
• Familiar with SPICE simulation tool (e.g., Cadence spectre, Synopsys Custom Compiler, Calibre)

· Strong Communication skills, high level of independence, self-motivation and good team player

Job Responsibilities:

1. Lead the analog design and development of either DDR or PLL IP (select one focus area), and collaborate with cross-functional teams to complete the full IP development cycle.

2. Provide support for mass production and debugging of the assigned IP.

3. Participate in the development of other SerDes-related IPs and coordinate tasks related to product integration.

Requirements:

1. Master's degree or above in Electrical Engineering, Microelectronics, or a related field; minimum 5 years of experience in analog circuit design.

2. At least 3 years of hands-on experience specializing in DDR or PLL design, with proven ability to lead projects independently and substantial tape-out experience.

3. Experience with FINFET processes is a strong advantage.

4. Proactive, detail-oriented, responsible, with a positive work attitude and strong communication skills; team player with a collaborative mindset.

Job Responsibilities:

· Design and implementation of mixed signal CMOS IP. Development cycle including circuit design, simulation, modeling, verification and bench characterization.

· Management products utilizing leading edge sub-micron CMOS technologies, e.g., 5/6nm

· Developing state of the art high speed mixed signal IP products that include op amps, comparators, bandgap, low-drop linear regulator, ADCs, DC-DC converters, and high bit-rate (Gbps) Serdes TX/RX.

Requirements:

· Bachelor or above degree in Microelectronic or Electronic and Information Engineering

· 5 years or above experience in the area of analog design

· Good knowledge in analog IC design in high speed Serdes, e.g., PLL, CDR, CTLE/DFE, TX driver etc.

• Solid understanding and experience in key analog layout considerations such as device matching, parasitic, noise coupling, floor planning, sensitive signal routing, current density and reliability considerations
• Familiar with SPICE simulation tool (e.g., Cadence spectre, Synopsys Custom Compiler, Calibre)

· Strong Communication skills, high level of independence, self-motivation and good team player

Job Responsibilities:

1. Lead the analog design and development of either DDR or PLL IP (select one focus area), and collaborate with cross-functional teams to complete the full IP development cycle.

2. Provide support for mass production and debugging of the assigned IP.

3. Participate in the development of other SerDes-related IPs and coordinate tasks related to product integration.

Requirements:

1. Master’s degree or above in Electrical Engineering, Microelectronics, or a related field; minimum 5 years of experience in analog circuit design.

2. At least 3 years of hands-on experience specializing in DDR or PLL design, with proven ability to lead projects independently and substantial tape-out experience.

3. Experience with FINFET processes is a strong advantage.

4. Proactive, detail-oriented, responsible, with a positive work attitude and strong communication skills; team player with a collaborative mindset.

JOB DESCRIPTIONOVERVIEWRambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Principal Engineer Analog Design to join our memory interface chip design team in Bangalore. Candidates will be joining some of the brightest inventors and engineers in the world to develop products that make data faster and safer. As a Principal Engineer Analog Design, the candidate will be reporting to Director Engineering and is a Full-Time position. The candidate will be leading the analog mixed signal circuit design activities for high-performance mixed signal chip products. Rambus memory interface chips team delivers the most advanced chipset solutions for server memory sub-system. This role gives opportunities to invent solutions to improve performance of next generation high-performance mixed signal products and learnings opportunities working through all the phases of chip product design all the way from concept to volume production.Responsibilities:As a Principal Engineer Analog Design in memory interface chip design team, you will Ownership of Analog/Mixed designs at chip and/or block level. Define optimal architectures to achieve competitive product specifications. Design, simulate and characterize high-performance and high-speed circuits (e.g. Transmitter, Receiver, LDO, PLL, DLL, PI circuits). Create high level models for design tradeoff analysis and behavior model for verification simulations. Create floorplan and work with layout team to demonstrate post extraction performance. Document analysis and simulation to show that design achieves critical electrical, timing parameters and pre-silicon verification flow. Mentor/Manage junior team members and cultivate a growth mindset among team to encourage collaboration & inclusion. Participate and drive post silicon validation, debug, and customer collaboration.Requirements/Qualifications: Masters with 8+ years (or PhD with 6+ years) of experience in CMOS analog/mixed-signal circuit design. Prior experience in some of the following circuits: Transmitter, Receiver (with CTLE, DFE), PLL, DLL, PI, LDO regulators. Good knowledge of design principles for practical design tradeoffs. Knowledge of high-speed chip to chip interfaces (memory PHY, SerDes) is a strong plus. Experience in modeling (Verilog-A, Verilog) and scripting is desirable. The position requires good written & verbal communication skills as well a strong commitment and ability to work in cross functional and globally dispersed teams.About RambusWith 30 years of innovation and semiconductor expertise, Rambus leads the industry with products and solutions speed performance, expand capacity and improve security for today's most demanding applications. From data center and edge to artificial intelligence and automotive, our interface and security IP, and memory interface chips enable SoC and system designers to deliver their vision of the future.Rambus offers a competitive compensation package, including base salary, bonus, equity and employee benefits.Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures. If you need assistance or an accommodation due to a disability, you may let us know in the application.Rambus does not accept unsolicited resumes from headhunters, recruitment agencies or fee-based recruitment services.For more information about Rambus, visit rambus.com. For additional information on life at Rambus and our current openings, check out rambus.com/careers/.,

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Job Overview:

We are seeking a senior analog engineer to join our team and play a key role in defining analog system design specifications and architectures for high-performance Ethernet PHY, gateway, and TSN switching chips.

• Develop and lead analog designs during product development.
• Collaborate with the engineering team to design and realize high-speed low-power small-area network chips.
• Responsible for the design and verification of analog and mixed-signal circuits, particularly CMOS signal processing circuits with expertise in areas such as RX (e.g., AFE, ADC), TX (Serializer, DAC), PLL, LDO, ESD/EMC suppression, etc.
• Support high-level functional development and verification of analog and mix-circuit circuitry.
• Cooperate with product definition, layout implementation, lab test, and verifications.

Required Qualifications:

• Master's degree or PhD with > 4 years' experience in high-performance analog/mixed-signal ICs.
• Proven experience in IC design including chip tape-out and lab evaluation of design.
• Solid experience in using EDA CAD tools and performing Analog Custom Layout.
• Experience in measuring IC performance and debug of design to correlate simulations to measurements.
• Deep understanding of fundamental concepts, including detailed transistor level design, device physics, control/feedback loop stability analysis.
• Direct project experience in at least one of the following areas is a plus: ADC-DAC design PLL or clock/freq generation design.
• Knowledge and experience in Verilog coding is a plus.
• Strong communication skills and good team player.

About Us:

Our company has over 15 years of experience developing competitive products and expanding into new markets such as automotive & unpiloted driving, China's intelligent manufacturing, rail transit, and intelligent grid building industry.